CreatingaBasicArchitecture Model

Creating a Basic Architecture Model

Tutorial Goals

Combine the blocks of the Hardware library.
Understand the connectivity and the flow.
Explore the processor and peripheral block parameters.
Generate statistics.

Model Location

The models are located in $VS/doc/Training_Material/Tutorial/Architecture_Exploration/Creating_Basic_System/.

Model for Part 1: Proc_DRAM.xml
Model for Part 2: Proc_DRAM_Bus.xml
Model for Part 3: Processor_Execution_Timing.xml
Model for Part 4: Refine_Processor.xml

Model Details

This model demonstrates the use of the Hardware Architecture Library in VisualSim. This session combines the basic building blocks and the associated infrastructure overhead.

Use this series of tutorials to understand how to connect and configure the blocks in a system model.

Part 1: Construct a Processor model and execution instructions

Figure 1 is a block diagram of the Basic Architecture Model.

Block??Diagram of the Basic Architecture Model

Figure 1: Block Diagram of the Basic Architecture Model

Figure 2 is a VisualSim model of the Basic Architecture.

VisualSim model??of the Basic Architecture Model

Figure 2: VisualSim Model of the Basic Architecture

List of Block used

Sl No	Library Block	Description
1	Digital ModelSetup > Digital	This Simulator is used to model protocols, hardware, and mapping of behavior to architecture. This simulator is used when the model is being triggered as an event or based on time. The Digital Simulator implements the discrete-event Model of Computation (MoC). This Simulator maintains a notion of current time, and processes events chronologically in this time. Click here for detailed description & examples.
2	Traffic Traffic >Traffic	Traffic block outputs a new Data Structure (DS) at time intervals specified by the "Time_Distribution" setting. A Data Structure is a transaction containing a list of Field Names + Values. Click here for detailed description and examples.
3	ExpressionList Behavior --> ExpressionList	The ExpressionList blocks execute a sequence of expressions in order. The expressions can use the data on all the Input ports, Memories (Global and Local), Parameters, Numerical values, and String Constants.
4	Text_Display Results > Text_Display	Display the values arriving on the input port in a text display dialog. This block buffers the display data and updates the screen after the buffer is full. Click here for detailed description and examples.
5	Architecture Setup Hardware Setup > Architecture_Setup	This block handles all the address mapping, routing, plotting, statistics, and debugging for the Hardware Modeling components. Click here for detailed description and examples.
6	Processor Processor Generator > Processor	The Processor block is used to model variations of commercial and proprietary processors. The goal of the block is to get accurate timing, data flow, throughput, and power computation of the processor. Click here for detailed description and examples.
7	Instruction Set Processor Generator > Instruction_Set	The Instruction_Set block can be used to create instruction references for the Processor. Click here for detailed description and examples.
8	RAM Memory > RAM	This block combines the operation of a basic memory controller (delay function) and the memory array. The block handles pre-fetch, read, write, refresh, and controller operations. The block can be interfaced to any Bus or Memory Controller. Click here for detailed description and examples.

Model Construction

Instantiate the above listed blocks into the block diagram.
Connections:

Connect the Traffic block to the ExpressionList block.
The ExpressionList block is connected to the Instruction input of the Processor.
Connect the Bus port of the Processor to DRAM. This requires two connections, one for either direction.
The Text_Display is connected to the Instr_Complete port of the Processor.

Setting block attributes

Traffic: Name to "Processor_DS" and Timed_Distribution to "Fixed"
Digital "Stop_Time" = 10.0
InstructionName in Instruction_Set block to "MyInstructionSet". This matches with the name in the Processor block.
In the Instruction_Set block, change the instruction IU_Add to Add. The Processor_DS has a default instruction in A_Instruction field of {"ADD","ADD"}.
Keep the defaults for the DRAM
Set the Expression block to modify the A_Destination and A_Hop to the name of the processor- "Processor_1". This is required for the Processor to know that the list of instructions is destined for itself.

Execution

Click the "GO" button to start the simulation.
Make sure you get an output on the Text_Display. If you do not, check the Reject port of the Processor.

Notes

Look at the list of parameters for the Processor, Instruction_Set, and DRAM.
Review the fields in the Processor_DS Data Structure. To understand the usage of each field, refer to the Block documentation.
Which stage of the pipeline does the Processor make a request to the DRAM?
Is the Processor pipeline clear? If not, refer to the documentation to know how it is executed.
What is the Cache_Miss parameter of the Processor cache lines?