Code File Location: VisualSim/actor/arch/Instruction_Set
The
Instruction_Set block provides the list of instruction, cycle count,
and the association to Execution Units for a specific processor. The
basic parts of the Instruction set are
1. List of identifiers and associated execution unit. The basic
units are of type INT and FP with a _ + integer. The other names
can be of any string value.
FullProc Unit1 Unit2 Unit3 ;
Unit1 INT_1 ;
Unit2 INT_2 ;
Unit3 FP_1 ;
2. Load/store width to cache. This is grouped with a begin
and end. Each row has a Read or Write, pipeline stage where used,
width in bits, Execution Unit with matrix (no space with
execution unit) containing the instruction range that are associated
with this width. All other instructions will not send a
request out to the cache.
begin
size_config
;
Read 6 64 INT_5[1:187] ;
Write 6 128 INT_5[188:500] ;
Read 6 64 mem_neon_uopld ;
end
size_config
;
3. Execution Unit Buffer size. This specifies the Queue Size of
each execution in the Processor block. The last column is the
number of instructions that can be waiting to be executed.
begin execUnit_config ;
Queue_Size INT_1 16 ;
Queue_Size INT_2 16 ;
Queue_Size INT_3 16 ;
end execUnit_config ;
4s. Execution Unit. There is the begin and end with the name. Each
instruction line will have a name and number of cycles (single value or
a range). Each Execution Unit listed above have a representation here.
begin INT_1 ;
Instr1 1 ;
Instr2 1 3 ;
end INT_1 ;
The following is a PowerPC example of
How the Instruction_Set block can be configured:
/* Instruction Set or File Path. */
ÞNote: The first word is the identifier. The rest list the unique types of Exec Units. This is an abbreviation that can be used in the pipeline to send the instruction to anyone of these Units. Alternate approach in the pipeline would be multiple lines in the stage with one per Unit type.
PPC IU BPU FPU VPU ;
ÞNote: The next 4 items (any number are possible) show the number of types of Execution Units for each type. Each name is associated with a Group of instructions. The type names can be INT or FP, followed by any suffix. There can be only 2 Execution Units defined per line. if you list more, a error will be generated.
IU INT_1 INT_2 ;
BPU INT_3 ;
FPU FP_1 ;
VPU
FP_2 ;
ÞNote: For each item in the above list, there is a Group of instructions. This can be the complete list or a representation to match the number of cycles.
begin INT_1 ; /* Group */
IU_add 1 ;
IU_shift 1 ;
IU_rotate 1 ;
IU_logical 1 ;
end
INT_1 ;
begin INT_2 ; /* Group */
IU_mux 6 ;
IU_div 19 ;
end
INT_2 ;
begin INT_3 ; /* Group */
*b 1 ;
l_s 1 ;
end
INT_3 ;
begin FP_1 ; /* Group */
FPU_s_add 3 ;
FPU_s_mul 3 ;
FPU_s_madd 3 ;
FPU_s_div 17 ;
FPU_d_add 3 ;
FPU_d_mul 3 ;
FPU_d_madd 3 ;
FPU_d_div 31 ;
end
FP_1 ;
begin FP_2 ; /* Group */
vpu_sim_int 1 ;
vpu_com_int 3 ;
vpu_fp 4 ;
end FP_2 ;
Notice how the very first line after the column labels, which starts with “PPC” references internal execution units that appear below in two stages:
Mnew Ra Rb Rc Rd Re ; /* Label */
PPC IU BPU FPU VPU ;
IU INT_1 INT_2 ;
BPU INT_3 ;
FPU FP_1 ;
VPU
FP_2 ;
Since BPU, FPU, and VPU have direct execution unit references, they could have named them directly. In this case, the first line could read “PPC IU INT_3 FP_1 FP_2”.
The IU (integer units) in the PPC line refers to INT_1 and INT_2 execution units, which are in turn defined below this line as:
begin INT_1 ; /* Group */
IU_add 1 ;
IU_shift 1 ;
IU_rotate 1 ;
IU_logical 1 ;
end INT_1 ;
begin INT_2 ; /* Group */
IU_mux 6 ;
IU_div 19 ;
end INT_2 ;
The IU line defines two execution units that are available, based on the instructions they execute. If the instructions are unique between INT_1 and INT_2, then the instruction being processed by the pipeline will select the execution unit, based on the instruction uniqueness. If the instructions are shared between INT_1 and INT_2, then the available processor will be selected, in essence out of order execution based on who is currently available (not true in this example).
If the instructions are unique for all execution units, typically true for smaller processors, then the first line can just list the execution units directly. As the above execution unit instruction lists indicate, one can start with:
begin INT_1 ; /* Group */
and finish with:
end INT_1 ;
These keywords append INT_1 to each instruction in the group, so they actually appear as “INT_1 IU_add 1” internal to the Instruction_Set block. One can use the Instruction_Set block to create arrays that could be referenced by other blocks in the model (Instruction_Set name is the memory reference, set to global), for example.
Each instruction can have a cycle count or a range with upper and lower limits. In the second case, a number is selected from a uniform distribution random number. The number of cycles of any one instruction cannot exceed 5000. See example below:
IU_add 1 ;
IU_shift 1 8 ;
IU_rotate 1 8 ;
IU_logical 1 ;
Refer Instr_Set Demo Model.
| Parameter |
Explanation | Type |
Example |
| Instruction_Set_Name | This
is an unique name that is used in the Processor block to identify the
Instruction set association. |
String | "Instruction_Set_Name" |
| Instruction_Set_Text | The
content can be in this window, XML File or text file. For a
XML
and text file, the path + File Name with extension is required. The
syntax for text window requires a space between all entries, especially
the ';'. |
String | - |
| Record_Set_Name | The block name for the Instruction Set as a RecordToken. One can access this Instruction Set as a global memory, containing a RecordToken with each line in Instruction_Set_Text represented as an ArrayToken. The name of each field in the RecordToken is the first StringToken in the ArrayToken version and if the name matches the previous entry, then the second ArrayToken StringToken is conatenated to create a unique field name for the resulting RecordToken. | String | "Record_Set_Name" |