Architecture

Hardware Setup / ArchitectureSetup
Block Name: ArchitectureSetup

Code File Location: VisualSim/actor/arch/Architecture_Setup

Description

This block handles all the address mapping, routing, plotting, statistics and debugging for the Hardware Modeling components. There can be multiple ArchitectureSetup blocks in a model. Each block instance must have an unique name. All Bus and Hardware blocks must be associated with one of the ArchitectureSetup. The block parameters provide the following operation:

o Data Structure Mapping: All the Architecture block utilize the Processor_DS data structure template. There are specified fields that are required for correct internal operations. If an alternate Data Structure with different field names are used, the Field_Name_Mapping maps the Data Structure field to the Processor_DS equivalent. The original data structure is retained in a field and will be available when the data structure is sent out through the Processor, DMA or DeviceInterface blocks.

o Routing Table: The Routing table is used to create a connectivity topology between devices connected together. The Routing_Table is defined in the ArchitectureSetup. 'Routing_Table' format is as follows:

Source_Node Destination_Node Hop Source_Port ;

If a VisualSim provided device is used or two buses are connected with a Bridge or a custom block is defined with a DeviceInterface block to interface to a Bus, then no entry is required in the routing table. All the paths in the flows are fully identified in the Routing Table. Bus internals, such as from Port_1 to Port_2 in Bus_1 does not need to be identified. Every block within the hardware architecture library sends out Hello messages at simulation time 0.0 to determine the node-to-node connectivity. Any entry missing will throw an exception saying the following source, destination pair is "missing" in the routing table. for more details on constructing the routing table, see below.

o Statistics Collection and Display: The 'Number of Statistics' specifies the number of times statistics will be accumulated during the simulation. To get good quality sampling of the simulation statistics, it is good to experiment with this number. 'Statistics_to_Plot' is a comma separated list of statistics that must match one of the Statistics Names. Each will be plotted as a separate dataset and will be available on the plots_out port. To view all the plots, add a relation on the output of the plots_out and type in the number of statistics for the _width parameter. The utilization is output on the util_stats_out while activity details is on the internal_stats_out port.

o Activity Tracing: The Listen_to_Architecture selector can play the activities of the selected component. Listen_to_Architecture_Options are None, All, Bus, Cache, Processor Pulldown selection. To view the traces, Select Listen To Block for this Architecture Setup.

Refer ArchitectureSetup Demo Model.

Hidden Parameters

The user can add the following hidden parameter by Right-click->Customize->Add. These parameters are not commonly used and provided to speed up the simulation run.

No_Field_Map: Disables mapping of input Data Structure fields to User Data Structures. The default is set to true. To enable Mapping of incoming Data Structure Fields to the Processor_DS, set to false.

No_Plotting: This is by default set to true. If this is set to false, no plotting values will be output.

Start_Cycle: The cycle to start listen to block. The default is -1. This allows a user to skip to a specific cycle count before listing in Listen to Block.

Hello Messages

The routing table is automatically constructed in VisualSim using a combination of "Hello" messages that are generated on all ports of every Architecture block in the library. The "Hello" message is generated at time=0.0, before any other transaction. The Hello message contains only 4 fields. If the processing in any block depends on certain fields not available in the "Hello" message, a filter must be set to remove it. The user can also create their own Hello messages to automatically update the Routing Table with custom blocks. Using the DeviceInterface block, addDeviceToBus or updating the Routing Table are preferred options. The format of the Hello Message is as follows:

{A_Address_Min_Max        = "/* Format: Min_Address,Max_Address. Example:201,300 */",
A_Destination           = "Architecture_1",
A_Hop             = "output",
A_Instruction              = "Hello",
A_Source             = "SDRAM"}

Automatic Routing Table Construction

The Routing Table is used by the Processor, Bus, Cache, DRAM, DMA_Controller and DeviceInterface blocks. Each Architecture Library block sends a “Hello” message to the block it is connected to at simulation time 0.0, to indicate the block name and port it was sent from. Each receiving block updates the ArchitectureSetup Routing Table with source, destination, hop, and port information; and computes the routing table. Transactions sent to/from Architecture Library blocks with A_Source, A_Destination, A_Hop fields will use the Routing Table to route Transactions to the proper destination.

For example, if the Processor sends a cache prefetch to the external DRAM, it would first pass through the Bus. The Bus port blocks would lookup the source port name (Port_Name), and the Transaction destination name (A_Destination) to get the next intermediate destination, or hop. In this case it would be the port connected to the DRAM. The port connected to the DRAM, would set the A_Hop field to the name of the DRAM, so the DRAM block can verify that the Transaction sent to it is correct. In this case, the user just connects the Processor, to the Bus_Port, the DRAM to another Bus_Port on the same Bus, and the Routing Table will determine the proper port to send a Transaction. No user entries are required in the Routing Table for a single Processor, Bus, Cache, DRAM model.

If a user wants to obtain the actual Routing Table, then use the RegEx function:

getRoutingTable(String Architecture_Name)

which will return a Transaction with Source + ‘_’ + Destination field names.

If a model contains multiple busses, use a Bridge block between them. The block connected to a DMA Dout port must be included in the Routing Table. See the DMA model example for the format. A Bridge block will merge the routing for each side of the bridge. Here are some rules of thumb for adding Architecture Library blocks to a model that influence the Routing Table:

1. Each Architecture Library block needs an unique name.

2. Processor cannot connect to more than one Bus Port of the same Bus, else a routing exception. Suggest disconnecting the extra connection.

3. User generated Transactions that set A_Source, A_Destination, also need to set A_Hop to the name of the Architecture Library block it is connected to. Otherwise, the Transction may be dropped.

4. If a Routing Table entry is missing, then an exception will indicate the Source and Destination missing. Manually enter this into the ArchitectureSetup Routing Table window. (More details below)

5. Use listen to port to see a transaction gets to the desired destination.

6. If you are constructing a custom component and attaching it to the Bus, use a DeviceInterface block to link the device and the Bus. The DeviceInterface block will automatically generate the required Routing Table Entries.

Manual Routing Table Entry

1. ArchitectureSetup Routing Table Window. Format is Source, Destination, Hop, Port. Hop is the next intermediate block name, such as “Port_1” if Transaction entering a Bus Port. Port is the name of the block output port name. It is important if a Bus Port block, since each Bus Port has two ports. Here is sample entry, third line reflects “Port_1”. First line are descriptions and ‘;’ needed at end of each line.

Source_Node Destination_Node Hop          Source_Port ;
MySource     MyDestination        MyNextBlock MyOutPort   ;
Processor      DRAM                  Port_1       bus_out     ;

2. RegEx can add entries from within the model. Here is how to add an entry (all strings):

addToRoutingTable (Architecture_Name, Source_Name, Destination_Name, Hop_Name, Source_Port_Name)

The print out will be Hop Source_Port Source_Node Destination_Node.

The example in (1) will look like:

addToRoutingTable (“Architecture_1”, “Processor”, “DRAM”, “Port_1”, “bus_out”)

Here is how to remove an entry from within the model (all strings):

removeFromRoutingTable (Architecture_Name, Source_Name, Destination_Name, Hop_Name, Source_Port_Name)

3. There are additional RegEx methods such as mergeBusTable RegEx functions, The Basic Technology documentation containing the list of RegEx functions has detailed explanation.

Parameter	Explanation	Type	Example
Architecture_Name	This is the name of the ArchitectureSetup block. This is the name that all the architecture conencted with this block will reference.	String	"Architecture_1"
Field_Name_Mapping	This text window manages all the External to Internal Field Mapping. The format is as follows: External_Field_Name Internal_Field_Name.	String	/* First row contains ColumnNames. */ External_Field_Name Internal_Field_Name ; A_Address A_Address ; A_Bytes A_Bytes ; A_Data A_Data ; A_IDX A_IDX ; A_Instruction A_Instruction ; A_Priority A_Priority ; A_Source A_Source ; A_Destination A_Destination ; A_Task_ID A_Task_ID ; A_Time A_Time ;
Routing_Table	The format is as follows: Source_Node Destination_Node Hop Source_Port.	String	/* First row contains Column Names. */ Source_Node Destination_Node Hop Source_Port ; Processor_1 Cache_1 Port_1 bus_out2 ; Cache_1 Processor_1 Port_2 output ; Cache_1 SDRAM_1 Port_2 output ; SDRAM_1 Cache_1 Port_4 output ; SDRAM_1 Processor_1 Port_4 output ;
Number_of_Samples	Number of Statistics to collect for the duration of the simulation time. '0' will not collect any statistics.	Integer	2
Statistics_to_Plot	Statistics_to_Plot is a comma separated list of statistics. Each entry must match one of the Statistics Names. If no plot output is desired, enter "NONE".	String	"Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max"
Internal_Plot_Trace_Offset	The Internal_Plot_Trace_Offset is used to offset the timing diagrams from each node or dataset in the state plots. The default is 2 units.	Integer	2
Listen_to_Architecture_Options	This is a selector for None, All, Bus, Cache, Processor Pulldown. Listen to Block on Architecture_Setup allows viewing of one or more architecture blocks in operation. To view the trace, select Listen to Block at this Architecture Setup.	-	Bus