Using the Interface

To create a new Verilog module, the following steps must be followed. More details are provided using examples.

• Drag a Verilog_Sim block from Full Library > Hardware_Language > Verilog. This is the Verilog setup parameters.
• Next drag a Verilog Cosim block from Full Library > Hardware_Language > Verilog.
• Configure the block parameters as follows:

1. Verilog_Module_Name is the name of the block or Source Code.
2. Verilog_File_Path is the absolute path of the Source Code. It can also be the relative path to the VS_C_Library. The Verilog module code is the top-level that needs to be interfaced with the rest of the system.

• Now, configure the ports.

1. Add as many input and output ports as required. Multiports are not supported.
2. Configure the Remote Types to the corresponding types in Verilog.

• Now execute from the Menu Bar, the Interface > Generate Wrapper and then Interface > Compile Wrapper in that order.
• Now add the rest of the system or connect this block to the rest of the system.
• You should now be able to simulate the model.