Verilog
Custom Coded Block – Verilog
VisualSim facilitates the user to use Verilog code through Verilog_Cosim.
This block allows the VisualSim model to use an application or program
written in Verilog. One can use the existing Verilog application in the
VisualSim model. VisualSim automatically generates code to wrap the
programs. This document provides details on how to create VisualSim
models that access Verilog application or program. All example models
given in this document are available under Verilog directory. To
complete this section, create utility on your OS and Verilog Simulator.
Types Supported
- The basic Verilog data types supported are: wire, reg, integer, real, and parameter.
- The corresponding VisualSim types are: integer, double, and string.
- Note that once code is generated it need not be repeated.
- The following table shows the native Verilog types and their corresponding java types.
Verilog Types
|
Corresponding Java Types
|
wire scalar
|
String
|
wire vector
|
String
|
reg scalar
|
String
|
reg vector
|
String
|
Integer
|
int
|
real
|
double
|
Table 1. Verilog types and their corresponding VisualSim types
Select the VerilogVpi input and output format. The following table provides the list of supported Verilog VPI formats.
Verilog Vpi input and output format
|
Return Description
|
vpiBinStrVal
|
String of binary chars [0,1,x, z]
|
vpiOctStrVal
|
String octal chars [0-7, X, x, Z, z]
X – When some of the bits are x.
x - When all the bits are x.
Z - When some of the bits are z.
z - When all the bits are z.
|
vpiDecStrVal
|
String of decimal chars [0-9]
|
VpiHexStrVal
|
String of Hexdecimal chars [0-f, x, X, z, Z]
X - When some of the bits are x.
x - When all the bits are x.
Z - When some of the bits are z.
z - When all the bits are z.
|
VpiIntVal
|
Integer value of the handle. Any bits x or z in the value of the object are mapped to zero.
|
VpiRealVal
|
Value of the handle as a double.
|
VpiStringVal
|
A string where each 8-bit group of the value object is assumed to represent an ASCII character.
|
Table 2. Verilog Vpi input/output format and Description
