Testing the Interface

To make sure that the interface is running properly on your machine, run the demo examples.

• Open the demo example model.xml from the following path:

For Windows: demo\Interfaces\Verilog\FullAdderWin

For Linux: demo\Interfaces\Verilog\FullAdderLinux

• Double-click on the Verilog module - Oscillator - and view the parameters.
• Right-click the Verilog module - stage1 - and select Open Block.
• Make sure you can see the Verilog source code.
• Click Interface > Generate Wrapper.
• Click Interface > Compile Wrapper.

If the compiling was successful, you get a message as follows:

The model compilation process was successful.

Now, click GO to run the simulation. You see a plot displaying results.