Preview

Reviewing a Pre-Built Model

The example model shown in Figure 1 is located under demo/Verilog/FullAdder directory. This model uses a Verilog_Cosim Block, which takes three different inputs and two outputs.

Section Using the Interface explains the steps involved in creating this model.

Figure 1. FullAdder model

Using and Configuring the Verilog_Cosim

This chapter explains on how to use and configure the Verilog_Cosim to interface Verilog code in VisualSim. The Verilog_Cosim is located in Full Library > Hardware_Language > Verilog. The block can be placed on the canvas in the same way as any other block. Once the Verilog_Cosim has been placed on the canvas, the block needs to be configured.

Configuring the Interface

Right-click the Verilog_Cosim block and select Customize > Configure. This menu is used to specify the Verilog location and file name.

The parameters are as follows:

Figure 2. Configuring the Verilog_Cosim block

• The parameter Verilog_Module_Name is the directory name for the block that is created under the base directory. The base for the Verilog_Module_Name of the block is always set to Verilog directory. Just the directory structure within this level is sufficient.
• The parameter Verilog_Module_Path specifies the location of the “. v” files which contain the definitions for the Verilog functions to interface with VisualSim. The absolute path for the file should be specified when they are located outside of the VisualSim Install Directory. Use only forward slash ‘/’ when specifying absolute path as VisualSim permits only forward slash to maintain platform independence.

Note: The Verilog file name without the “.v” extension should match the Verilog Module Name.

Configure the ports in the Verilog_Cosim Block

• Right-click Verilog_Cosim and select Customize > Port.
• Configure the input / output port names and types.
• The first time the Customize > Port is selected, the following window appears.

Figure 3. Configure ports for Verilog_Cosim block

Click Add in Figure 3 to view the window in Figure 4. Double-click on the Name field and enter the field name. Select input or output type and the VisualSim data type (from the “Type” column).

Figure 4. Configure ports for Verilog_Cosim block

Now add the Remote Type with the Verilog type [width of the port]; Verilog PLI type.

The Remote type should be in double quotes. Here the format for specifying the Remote Type is:

Format: “Verilog Data types [width of the port]; Verilog PLI Format”

Example: “wire [0:3]; vpiBinStrVal”

• Add as many Ports, as required, by repeating the above steps.
• The following table shows the Verilog data types and their equivalent java types.

Table 1 Verilog Arguments and Equivalent Java Port Types

Generating Verilog Wrapper Functions

After the Verilog_Cosim block is configured, the interface template can be generated and compiled, which enables execution of the Verilog_Cosim block in VisualSim. Use the GUI menu Interface > Generate Wrapper shown in Figure 5 to generate Verilog Wrapper. Use the GUI menu Interface > Compile Wrapper in Figure 5 to compile the Verilog Code.

Figure 5. Menu Bar View to Select Generator

• Successful compilation of the source files creates a Jni<Verilog_Module_Name> .dll (or .so) file under blocks directory. The file extension “. Dll or .so” indicates that the file is a link library.

Note: Open the “vsout.txt” file under the Library Directory to check for any errors that occurred during the compilation process. This could help correct any mistakes in the interface Verilog code.

• The blocks directory has been provided under demo\interfaces\Verilog directory to hold “. Dll or .so” files, which is in the PATH. This is where the example system wrappers are stored. The user created wrappers are stored in the setting provided by the user.

Running the Executable Model

The Text_Display (Non-Buffered) block can be dragged on to the canvas from Result > Text. Similarly, the Const input block can be obtained from the Full Library > Math Operations > Math and Trig. Control-click to create the relations.

Connect all the blocks as shown in the Figure 1 and then add an Untimed Digital simulator (from ModelSetup) and change the number of iterations from 0 to 1 by double-clicking the Untimed Digital simulator.

Click the “Run” button in the IDE or press Ctrl+R to execute the model.

Checking the Codes

Codes for the respective Verilog demo model are saved as .v file located in the following directory:

demo\Interfaces\Verilog\(Name of the demo model)\(Name of the file).v

For ex: demo\Interfaces\Verilog\OrGateWin\orgate.v