Timing Diagram
Hardware Setup / TimingDiagram
Block Name: TimingDiagram
Code File Location: VisualSim.actor.lib.gui.Arch_State_Plot
The Timing Diagram block enables the user to view a Gantt chart of the activity associated with the main Architecture devices- Bus, Cache, DRAM, AXI, LPDDR and CycelAccurateDRAM There can be multiple instances of this block in a single model. Each block instance will produce a unique plot. This block is used in conjunction with the ArchitectureSetup.
Refer TimingDiagram Demo Model.
Parameter |
Explanation |
Type |
Example |
Proc_Name |
Name of the Processor instance. |
String |
"Processor_1" |
Bus_Name |
Name of the Linear Controller or Bus Controller instance. |
String |
"Bus_1" |
Cache_Name |
Name of the Cache instance. |
String |
"Cache_1" |
DRAM_Name |
Name of the DRAM block instance. The DRAM block can be used as a Flash, DRAM, SDRAM and SRAM. |
String |
"SDRAM_1" |
AXI_Name |
Name of the AXI instance. |
String |
"AXI_1" |
Memory_Controller_Name |
Name of the LPDDR instance. |
String |
"LPDDR_1" |
HW_DRAM_Name |
Name of the CycleAccurateDRAM instance. |
String |
"SDRAM" |
Sim_Time |
Length of the simulation. This must be linked to the top-level simulation stop-time. |
Double |
10000.0 |
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