Utility

Timing Diagram - The Timing Diagram block enables the user to view a Gantt chart of the activity associated with the main Architecture devices- Bus, Cache, DRAM and Memory.

Register_Expr_N - This block enables the user to output the incoming Token at the clock trigger.

Register_N - This is a clock gating device with a register for holding the incoming values.

4_LUT - This is a 4 Input Look-up Table that can be used for evaluating.

VCD Writer - This block accepts data structures on the input and outputs the selected fields as signals to be used in Verilog. The final output of this block is a vcd file.

Created with the Personal Edition of HelpNDoc: Produce Kindle eBooks easily