FullAdder Model

The following section explains the creation of Verilog model in VisualSim. A FullAdder model is a 4-bit adder ripple-carry adder. It takes two 4-bit binary, one 1-bit binary inputs and one 4-bit binary, and one 1-bit binary output.

Drag the Verilog_Cosim block from Full Library > Script_Language_Interface > Verilog to the editor space.

FullAdder??model-verilog

Figure 1. FullAdder Model

Right click on the actor and select Configure Arguments. Configure the parameter values as shown in the figure. The parameters are as follows:

The Verilog_Module_Name is the model name in Verilog.

For example, ”FullAdder”.

The Verilog_Module_Path is the path to the Verilog source files (*.v).

For example, “D:/VisualSim/VS930/demo/interfaces/Verilog/FullAdder/fulladd4.v”

Here the “*.v” file name should be same as the Verilog module name in the user Verilog code.

Configuring the Verilog_Cosim

Figure 2. Configuring the Verilog_Cosim

Configure the ports in the Verilog_Cosim Block:

Select the context menu of the Verilog_Cosim and select Customize > Ports.
Configure the input / output ports, type of the ports, and Verilog Data types in the Remote type Column.

Configure ports for the Verilog_Cosim

Figure 3. Configure ports for the Verilog_Cosim

Now save the model before code generation.
Click Interface > Generate Wrapper for code generation.
Click Interface > Compiler Wrapper for code compilation of the source files.
A new folder named “FullAdder” will be automatically created under Verilog directory, if it does not exist already. Otherwise it overwrites the existing generated files with the new files.
Successful compilation of the source files creates a Jni<Verilog_Module_Name> .dll/.so file under the blocks directory. The file extension “. Dll or .so” indicates that the file is a link library.

Note: Open the “vsout.txt” file under the Library Directory to verify the errors that could have caused any unsuccessful compilation process. These could help to correct any mistakes in the interface code.

The blocks directory has been provided under Verilog directory to hold “. Dll” files, which is in PATH.
Drag the Text_Display (Non-buffered) block from the Result > Text. Similarly the Const input block can be obtained from the Full Library > Math Operations > Math and Trig. Control-click to create the relations from the toolbar.
Connect all the blocks as shown in Figure 1.
Add a Digital simulator (located under ModelSetup). Double click the Digital simulator and change the number of iterations from 0 to 1.
To run the FullAdder model, click the run button in the IDE or press Ctrl+R.

FullAdder Model

Figure 4. FullAdder Model

The Verilog code of this model is located in the directory:

demo\Interfaces\Verilog\FullAdderWin\fulladd4.v

The codes of the fulladd4.v will be displayed as follows:

`timescale 1ns / 1ns

module addbit (sum, co,a, b, ci);

input a, b, ci;

output sum, co;

wire a, b, ci, n1, n2, n3;

wire sum, co;

xor    (n1, a, b);

xor (sum, n1, ci);

and    (n2, a, b);

and    (n3, n1, ci);

or   (co, n2, n3);

endmodule

module fulladd4(sum,c_out,a,b,c_in);

input a,b;

input c_in;

output sum;

output c_out;

wire [0:3]a,b;

wire [0:3]sum;

wire c_in,c1,c2,c3;

addbit a1(sum[0],c1,a[0],b[0],c_in);

addbit a2(sum[1],c2,a[1],b[1],c1);

addbit a3(sum[2],c3,a[2],b[2],c2);

addbit a4(sum[3],c_out,a[3],b[3],c3);

endmodule

Full Adder Model

FullAdder Model