Part 5 - Multi-Channel DMA

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Multi-Channel DMA


Tutorial Goals

The following is a summary of the concepts you will learn in this session.

  1. Use Statistical SystemResource blocks to define the resources in a system.
  2. Use the channel blocks to define distributed activities.
  3. Manage the Cache/SDRAM usage information with VisualSim memory elements.

Target


In this section we focus on the effect of using a shared DMA for memory access. The model has multiple resources that consume time in the flow. There are some devices with direct connections to the DMA and others are connected to it via a Bus. This tutorial helps the user to understand the TimedQueues and Channels, and the generation of latency plots.

Dual????Processor System Block Diagram

Figure 1: Block Diagram of the Multi-Channel DMA Design

VisualSim Tutorial Model Location


Open this model in VisualSim from the following location:

File->Open $VS/doc/Training_Material/Tutorial/WebHelp/Tutorial/Performance_Modeling/DMA_Exercise.xml  


Model Objectives


  1. Identify the resources and the flows.
  2. What block should be used to model the DMA?
  3. What is the traffic generation schemes to be deployed?
  4. Make hit-and-miss decisions.

Blocks Used

  1. Traffic >Traffic
  2. Full Library > Defining Flow > Processing
  3. Behavior > Expression_List
  4. Behavior > IN
  5. Behavior > OUT
  6. Behavior > Fork
  7. Results > TextDisplay
  8. Results > TimeDataPlotter
  9. Full Library > Resource >Timed-Queue >TimedQueue
  10. Full Library > Resource > Channel and Pipeline >Channel
  11. Full Library > Resource > Channel and Pipeline > Channel_Release

Model Construction

  1. Parameters for the model are:
    1. µP1- Speed=500MHz, Data Size=24 bytes, ID="µP"
    2. DSP1- Speed=266MHz, Data Size=16 bytes, ID="DSP"
    3. OH1- Inter-arrival time between 100-200 µs, Data Size= 64 bytes, ID= "OH1"
    4. OH2- Inter-arrival time of 150 µs, Data Size= 8 bytes, ID= "OH2"
    5. DMA- packet size=64 bytes, buffer=32
    6. Bus- Speed=266MHz
    7. Cache- Speed=266MHz
    8. SDRAM- Speed=133MHz
  2. Model Variables: How do you include this in the model?
    1. DMA speed =< 266 MHz
    2. Number of DMA channels = 4-16
    3. Cache hit ratio = 0.7-0.9
  3. Simulation Output
    1. Plot the request latency from µP and DSP when accessing SDRAM.
    2. Print the complete DS after the data has been accessed. In this case, assume all transactions to be a Write. So, there is no return path.
  4. Analysis
    1. Is there a relation between the cache hit ratio and the miss latency?
    2. Which parameter (Cache hit ratio, DMA speed and DMA channels) has the biggest impact on the latency?


Construction Steps

The Construction of the above model in a step-by-step manner is described below.

  1. Open a new block diagram by selecting File > New > Block Diagram.
  2. Drag the Digital block (ModelSetup > Digital) onto the block diagram. Make parameter "StopTime = 5.0e-6” (user-defined value). Maintain the default for all other values.
  3. Setup the Parameter (ModelSetup > Parameter=) as shown below:

           Bus_Speed                = 266

           UP_Speed_Mhz         = 500.0

           DSP_Speed_Mhz      = 266

           SDRAM_Speed         = 133

           DMA_Speed             = 500

           DMA_Packet_Size    = 32

           Cache_Speed           = 266

           Cache_Hit_Ratio       = 0.9

  1. Setup the Traffic using Traffic (Traffic >Traffic) for µP, DSP, OH1, and OH2.

Multi-DMA_step1

Figure 1. Traffic Generation

  1. Drag the Processing block from Full Library > Defining_Flow > Processing to define the transaction Field (by double-clicking the block). Setup the field values such as Source_Name, Transaction_Bytes, Hit_or _Miss, and Timing Delay.
    1. µP1 and OH1

Assign the Field value for uP1 and OH1

Figure 2. Parameter value for µP1 and OH1

Parameter????for processing_MultiChannel DMA

Figure 3. Assign the Field value for DSP and OH2

  1. Drag the TimedQueue block (Ful Library > Resource > Timed-Queue  > TimedQueue) and pop-out the token according to the Transaction_Bytes / bus_speed_Mhz.
  2. Setup the DMA block (Full Library > Resource > Channel and Pipeline > Channel) and the DMA Release block (Ful Library > Resource > Channel and Pipeline > Channel_Release).

MultichannelDMA_Step4

Figure 4. DMA Access

Parameters for????Channel_Basic

Figure 5. Channel Parameter Setup

  1. Pass the Token through the Virtual Connection (Behavior > IN and Behavior  > OUT) to the Cache containing TimedQueue which triggers the token according to the Transaction_Bytes / Cache_speed_Mhz.

Cache????Access

Figure 6. Cache Access

  1. Verify the Cache Hit or Miss using Decision block (Behavior > Expression_List).

If Cache Hit, display the output

If Cache Miss, access the SDRAM

Cache Hit or Miss Calculation:

    Result_A  =   (input. Hit_or_Miss <= Cache_Hit_Ratio)?True: False

  1. In case of Cache_Miss, pass the token into the SDRAM (TimedQueue) and Pop-out the Token according to the Transaction_Bytes / SDRAM_speed_Mhz.

Cache Miss????access the SDRAM

Figure 7. Cache Miss access the SDRAM

  1. Derive the latency for Cache_Miss (uP_Cache_Request_Latency, DSP_Cache_Request_Latency) and Cache_Hit and plot it.

uP_Cache_Request_Latency    = TNow - input.TIME

DSP_Cache_Request_Latency = TNow - input.TIME

Multi Channel DMA Design

Figure 8. Multi Channel DMA Design