MoP
Code File Location: VisualSim/actor/arch/Processor_Blocks
This
blocks is used to emulate the hardware and software part of MoP cache
in the processor architecture model. Hardware blocks such as input
buffers, cache hit/miss and processing
are implemented
using the script code. Similarly the software parts such
as replacement, flow control and branch flushes are implemented
in the script code.
MoP
Cache holds the Macro op as the instructions gets decoded in the
pipeline. MoP enables reduction in pipeline latency by bypassing the
decode stage and forward the Macro instructions to rername stage.
The following is the sequence of operation:
MoP Update:
1. The decoded instructions will be loaded to the input queue and the entries are updated in the cache
2. If thre is an overflow or the cache is full, the least used
instructions will be removed and the new instructions will be loaded in.
MoP access:
1. Set of addresses will be loaded in the queue.
2. If the addresses are hit then the MoPs will be read and issued to
MUX block, else the miss response will be sent to fetch unit.
3. If there is branch flush then the current processing and the queue contents will be discarded.
BPU unit issues the standard "Processor_DS" data structure.
"A_Address", "A_Instruction_Addr", "A_Destinaton" is the necessary input field.
| Parameter |
Explanation | Type |
Example |
| MOP_Name | This is a unique name of this block. No other Architecture, Virtual_Machine, Scheduler or Smart_Resource can have this name in a model. The memory name is used to identify this destination. | String | "Core_1_MoP" |
| Core_Speed_Mhz | Speed of the processor core in Mhz. | Double | 1200.0 |
| MOP_Entries | MoP cache size as number of entries | Integer | 1500 |
| Input_Buffer_Size | size of the input queue |
Integer |
16 |
| Instr_Feed_DB_Name | Database name which contains the disassembly trace |
String |
"Instruction_Cache_Feed" |
| Arm_Mode | determines the instruction size |
Boolean | true /*true - arm mode, false - thumb model*/ |
| Width_Bytes | cache access width bytes |
Integer | 16 |
| Power_Manager_Name | Name of the power table, this will enable the power observation of this block with required configuration in power table. "none" will diable the power feature |
String | "Manager_1" |
| Debug_Enabe |
Used for internal debugging | Boolean |
false |
| Port | Explanation |
| to_Fetch |
This port connects this block to the Fetch stage or the next stage intermediate blocks. This port is on the left side of he block(West). |
| Frm_Fetch | This port connects this block with the Fetch stage or the next stage intermediate blocks. This port is on the left side of he block(West). |
| Frm_Commit | This port connects this block with the Commit stage. This port is on the bottom side of he block(South). |
| Frm_Decode |
This port connects this block with the Decode stage. This port is on the bottom side of he block(South). |