Decode Stage

Cycle_Accurate_Processor / Decode_Stage
Block Name: Decode_Stage

Code File Location: VisualSim/actor/arch/Processor_Blocks

Description

This blocks is used to emulate the hardware and software part of decode unit in the processor architecture model. Hardware blocks such as Decode queue, N way instruction decoding and branch flushing are implemented using the script code. Similarly the software parts such as Unconditioanl branch identification and address calculations are implemented in the script code.

Operation

Decode block runs in parallel with all other blocks to enable pipelined operation in the architecture.

The following is the sequence of operation:

Instruction decoding:

    1. Set of instructions fetched from the I cache will be loaded to Decode queue.

    2. When the decoder is available the instructions will be taken from the deocde queue and processed.

    3. if the instuctioin is unconditioanl branch
        - Target address will be calculated or refered from the compiled argument
        - The next address in the fetched sequence will be verified against the Target address.
        - If it is not correct then the branch flush will be initiated, and the instructions upto the branch will be forwarded to next stage.
        - If it is correct then entire decoded instructions will be forwarded to next stage.

    4. if there is no unconditional branch then the entire decoded instructions will be forwarded to next stage.

Branch Flush:

    1. A hard flush (branch penality) will be issed to BPU unit, Fetch unit, Mop unit and the Mux unit.

    2. BPU will generate targeted sequence on misprediction.

    3. Fetch unit and Mop unit will discard the current processing and its queue contents

    4. MUX will discard the previously loaded instructions from MoP cache if any.

Data Structure Fields

BPU unit issues the standard "Processor_DS" data structure.

"A_Address", "A_Instruction ", "A_Instruction_Addr" and "Operands" are the necessary fields.

Parameter	Explanation	Type	Example
Decode_Unit_Name	This is a unique name of this block. No other Architecture, Virtual_Machine, Scheduler or Smart_Resource can have this name in a model. The memory name is used to identify this destination.	String	"Core_1_Decode"
Core_Speed_Mhz	Speed of the processor core in Mhz.	Double	1200.0
N_Way_Decode	Number of decode ways	Integer	4
Decode_Queue_Size	Size of the decode queue	Integer	32
Decode_Queue_Name	Name of the decode queue	String	"Core_1_Decode_Q"
Power_Manager_Name	Name of the power table, this will enable the power observation of this block with required configuration in power table. "none" will diable the power feature	String	"Manager_1"
Debug_Enable	Used for internal debugging	Boolean	false

Port	Explanation
Decode_inp	This port connects this block to the Fetch stage.
to_Fetch	This port connects this block to the Fetch stage.
Frm_MUX	This port connects this block to the MUX block or Rename block.
to_MUX	This port connects this block to the MUX block or Rename block.
to_Branch	This port connects this block to the Branch prediction stage.

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