Fetch Unit
Code File Location: VisualSim/actor/arch/Processor_Blocks
This
blocks is used to emulate the hardware and software part of fetch unit
in the processor architecture model. Hardware blocks such as input
fetch queue and the output issue queues are implemented
using the script code. Similarly the software parts such as MoP cache
lookup, outstanding fetch issues, preassure back flow control, and flow
prediction between MoP and Decode flows are implemented in the script
code.
Fetch Unit runs in parallel with all other blocks to enable the pipelined instruction fetch in a processor architecture.
The following is the sequence of operation:
Instruction fetch:
1. Set of addresses issued by the Branch unit will be loaded into the Fetch queue.
2. On the availability of resource and the queue occupancy the block
will fetch instructions from L0 cache or MoP cache if it is designed,
otherwise it will fetch from the L1 instruction cache.
- if the L0 or MoP cache is designed,
i) if hit then
the next address sequence will be loaded and issued to L0 or MoP cache.
ii) if miss then the same address sequence will be issued to L1 cache.
iii) in
either case of fetching the ordered flow is maintaned to support out of
order fetch completion at the MUX (Decode flow from L1 cache and L0 or
MoP flow will be the inputs to MUX).
Click here to read the MUX documentation
- if there is no L0 or MoP cache,
i) Multiple
request will be sent to L1 cache based on the outstanding fetch
configuration.
ii)
Once the fetch is completed the instructions will be loaded to Decode
queue.
4. if the input queue is full, the block will back preassure the previous stage to enable pipeline stall.
Branch Flush:
If there is branch flush due to miss prediction then the pipeline flush
will discard the current processing, issued fetch and the queue
contents.
Standard "Processor_DS" data structure.
"A_Instruction_Addr" is the necessary input field.
| Parameter |
Explanation | Type |
Example |
| Fetch_Unit_Name | This is a unique name of this block. No other Architecture, Virtual_Machine, Scheduler or Smart_Resource can have this name in a model. The memory name is used to identify this destination. | String | "Core_1_Fetch" |
| Core_Speed_Mhz | Speed of the processor core in Mhz. | Double | 1200.0 |
| Fetch_Queue_Entries | Input queue size |
Integer | 16 |
| Fetch_Width |
No of bytes to fetch in a sinle cycle, it determines the number of instructions to fetch |
Integer | 32 |
| Mode | Determines whether ARM mode or THUMB mode |
Boolean |
true /* true - Arm mode, false - THUMB mode*/ |
| Fetch_threshold | Number of Outstanding instruction fetch to L1 cache |
Integer | 2 |
| Cache_Name | L1 instruction cache name |
String | "Core_1_L1" |
| MOP_Name | Mop cache name | String | "Core_1_Mop" |
| Power_Manager_Name | Name of the power table, this will enable the power observation of this block with required configuration in power table. "none" will diable the power feature |
String | "Manager_1" |
| Debug_Enable |
Used for internal debugging |
Boolean |
false |
| Port | Explanation |
| Frm_Branch | This port connects this block to the Branch predictor stage or the intermediate blocks for previous stage. This port is on the right side of the block(West). |
| to_Branch | This port connects this block with the Branch predictor stage or the intermediate blocks for previous stage. This port is on the right side of the block(West). |
| Frm_I_Cache | This port connects this block with the L1 I cache. This port is on the bottom side of he block(South). |
| to_I_Cache | This port connects this block with the L1 I cache. This port is on the bottom side of he block(South). |
| Frm_Mop | This port connects this block with the MoP cache. This port is on the bottom side of he block(South). |
| to_Mop | This port connects this block with the MoP cache. This port is on the bottom side of he block(South). |
| to_Decode | This port connects this block to the Decocde stage or the intermediate blocks of next stage. This port is on the left side of the block(East). |
| Frm_Decode | This port connects this block to the Decocde stage or the intermediate blocks of next stage. This port is on the left side of the block(East). |
Code File Location: VisualSim/actor/arch/Processor_Blocks
This blocks is used to emulate the MUX logic in the model. It will combine 2 independent flows and it will link the flow based on the Flow select details from fetch unit.
MUX
will enable flow control to obtain packets from both the flows and link
it to the output based on a control variable ("MUX_Select").
The following is the sequence of operation:
1. Packets from both the flow will be loaded in MUX input, the selection of flow is based on the MUX_Select variable
2. if the packet is not ready yet in the expected flow, then the MUX
will block the entire flow untill the packet arrives.
| Parameter |
Explanation | Type |
Example |
| Mux_Name | This is a unique name of this block. No other Architecture, Virtual_Machine, Scheduler or Smart_Resource can have this name in a model. The memory name is used to identify this destination. | String | "Core_1_MUX" |
| Mop_Queue_Name | Name of MoP buffer |
String |
"Core_1_MOP_Q" |
| Mop_Queue_Size | queue size of Mop buffer |
Integer | 16 |
| Debug_Enable |
Used for internal debugging |
Boolean |
false |
| Port | Explanation |
| frm_Decode | This port connects this block to the Decode stage. |
| to_Decode | This port connects this block to the Decode stage. |
| MoP_Buff_in | This port connects this block to the MoP cache. |
| MoP_Buff_Out | This port connects this block to the MoP cache. |
| MoP_Update | This port connects this block to the MoP cache. |