Memory

RAM - This block combines a basic memory controller (delay function) and the memory cells to form a memory device.

Memory Controller - Implementation of all the DDR specification including DDR, DDR2, DDR3, LPDDR, LPDDR2.

CycleAccurate_DRAM - Functional and cycle-accurate Implementation of SDR-DRAM, DDR-DRAM, DDR2-DRAM, DDR3-DRAM, LPDDR-DRAM and LPDDR2-DRAM.

Integerated Cache - Used as L1 (Instruction or Data), L2 and L3 cache.

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