Branch Predictor
Code File Location: VisualSim/actor/arch/Processor_Blocks
This
blocks is used to emulate the hardware and software part of branch
prediction in the processor architecture model. Hardware blocks such as
target buffers, counters, Return address stack (RAS) and state machines
are implemented
using the database and script code. Similarly the software parts such
as branch prediction algorithm and branch table updates are implemented
in the script code.
Branch
Predictor Unit (BPU) is a standalone block which runs in parallel with
all other blocks in the architecture. BPU will initiate the
processor flow using the global variable "Initial_PC" (it will be
set during the initialization) as the starting address (PC) of the
initial instruction.
The following is the sequence of operation:
Address issue:
1. Set of addresses will be generated from the PC value.
2. Generated address will be checked against the branch target buffers (BTB).
3. if there is an entry in the BTB and the algorithm predicts that
branch will be taken, then the sequence of address up to branch address
is issued to the fetch queue.
- The next PC will be the target address and the operation continues from step 1.
4. if there is no entry or the algorithm predicts the branch will not
be taken, then the address of window size will be issued to the fetch
queue.
- The next PC will be the consecutive address and the operation continues from step 1.
Branch Update and prediction:
1. Branch instructions from the processor pipeline will be forwarded to BPU unit.
2. Branch informations will be loaded to the BTB buffers (both main
Buffers and L1 buffers) and function call return address will be loaded
to RAS stack.
3. Branch prediction is performed based on the algorithm.
i) One bit predictor - If the last branch is taken then the current prediction is taken and vice versa.
ii) 2 bit state machine - based on the last execution the state will be updated as towards "taken" or towards "not taken"
BPU unit issues the standard "Processor_DS" data structure.
A_Instruction_Addr will be th important output field.
| Parameter |
Explanation | Type |
Example |
| BPU_Name | This is a unique name of this block. No other Architecture, Virtual_Machine, Scheduler or Smart_Resource can have this name in a model. The memory name is used to identify this destination. | String | "Core_1_BPU" |
| Core_Speed_Mhz | Speed of the processor core in Mhz. | Double | 1200.0 |
| Instruction_Window_Size | No of bytes per cycle. (determines the number of addresses to be issued) |
Integer | 64 |
| Mode | Determines whether ARM mode or THUMB mode |
Boolean |
true /* true - Arm mode, false - THUMB mode*/ |
| L1_BTB_Entries | Size of the Level 1 target buffer |
Integer | 64 |
| Main_BTB_Entries | Size of the Main target buffer |
Integer | 8000 |
| RAS_Size | Size of the Address stack |
Integer | 16 |
| Power_Manager_Name | Name of the power table, this will enable the power observation of this block with required configuration in power table. "none" will diable the power feature |
String | "Manager_1" |
| Port | Explanation |
| to_Fetch |
This port connects this block to the Fetch stage or the next stage intermediate blocks. This port is on the left side of he block(East). |
| Frm_Fetch | This port connects this block with the Fetch stage or the next stage intermediate blocks. This port is on the left side of he block(East). |
| Frm_Commit | This port connects this block with the Commit stage. This port is on the bottom side of he block(South). |
| Frm_Decode |
This port connects this block with the Decode stage. This port is on the bottom side of he block(South). |