Execution Unit
Code File Location: VisualSim/actor/arch/Processor_Blocks
This
blocks is used to emulate the hardware anad software part of Execution
unit in the processor architecture model. Hardware blocks such as issue
queues, processing units, AGU, and registers
are implemented
using the database, server and script code. Similarly the software
parts such
as flow control, branch flush and queue handling are implemented
in the script code.
Execujtion
contains 2 levels of flow, the input instructions will be loaded in the
assciated issue queues then the istructions will be executed based on
the availability of the processing elements.
The following is the sequence of operation:
Instruction processing:
1. Dispatched micro instructions will be loaded in the issue queue one
after another. if the queue is full then the back preassure will be
issued to enable pipeline stall.
2. Based on the availability of the processeing elements the queue will be poped and issued to the execution units.
3. Load/store instruction will issue fetches to D cache , and the queue will be blocked if the maximum outstanding request is reached.
4. once the instructions execution is completed then the corresponding
instructions will be moved to commit stage.
Branch Update and prediction:
1. if there is a conditional branch miss predicted, then the loaded
instructions and the processing instructions will be discarded.
BPU unit issues the standard "Processor_DS" data structure.
"A_Address", "A_Instruction ", "A_Instruction_Addr" and "Operands" are the necessary fields.
| Parameter |
Explanation | Type |
Example |
| Core_Name | This is a unique name of this block. No other Architecture, Virtual_Machine, Scheduler or Smart_Resource can have this name in a model. The memory name is used to identify this destination. | String | "Core_1" |
| Core_Speed_Mhz | Speed of the processor core in Mhz. | Double | 1200.0 |
| Exec_Units | Available Units for Processing |
Array | {"INT","FP","LS"} |
| Issue_Queue_Length | size of common issue queue for each exec units |
Array |
{15,15,15} |
| No_of_Single_Cycle_INT_Units | Total number of Single cycle integer units |
Integer | 3 |
| No_of_Branch_Units | Total number of branch unts | Integer | 1 |
| No_of_Multi_Cycle_INT_Units | Total number of multi cycle integer units | Integer | 1 |
| No_of_FP_Units | Total number of floating point units |
Integer |
2 |
| No_of_LD_ST_Units |
Total number of load store units |
Integer |
2 |
| Power_Manager_Name | Name of the power table, this will enable the power observation of this block with required configuration in power table. "none" will diable the power feature |
String | "Manager_1" |
| Port | Explanation |
| input |
This
port connects this block to the Dispatch stage. |
| Flow_Control | This port connects this block to the Dispatch stage. |
| output | This port connects this block to the Commit stage. |
| to_D_Cache |
This port connects this block to the D cache. |
| frm_D_Cache |
This port connects this block to the D cache. |