Dispatch Stage
Code File Location: VisualSim/actor/arch/Processor_Blocks
This
blocks is used to emulate the hardware and software part of dispatch
stage in the processor architecture model. Hardware blocks such as
input queue and unified issue queue/ Reservation station / Instruction
window
are implemented
using the script code. Similarly the software parts such
as dependency ordering, execution unit allocation , flow control and
branch flushes are implemented
in the script code.
Dispatch
unit recieves the micro instructions and process them to identify the
depenency and the corresponding execution unit, then it will be issued
to specic Issue queue based on the availability of the resources.
The following is the sequence of operation:
Micro instruction handling:
1. Set of micro instructions will be loaded to the input queue
2. When the dispatch unit is free, the micro instructions will be taken
and analyzed to identify the dependency.
3. The instructions without any dependency will be loaded and thier execution units will be identified
- If the corresponding resource (Issue Queue) is available then the instruction will be dispatched, otherwise it will be maintained in the reservation station.
4. If
the instuction is dependent on the some other instructions then the
micro op will be loaded in the reservation station and dispatched later
when the instruction is ready to execute.
Branch flush:
1. if there is a conditional branch the instructions that are already
loaded in the queue and the reservation station will be discarded.
BPU unit issues the standard "Processor_DS" data structure.
"A_Address", "A_Instruction ", "A_Instruction_Addr","Dependency","ID_Order" and "Operands" are the necessary fields.
| Parameter |
Explanation | Type |
Example |
| Dispatcher_Name | This is a unique name of this block. No other Architecture, Virtual_Machine, Scheduler or Smart_Resource can have this name in a model. The memory name is used to identify this destination. | String | "Core_1_Dispatch" |
| Core_Speed_Mhz | Speed of the processor core in Mhz. | Double | 1200.0 |
| Instruction_Win_Entries | Instruction window size |
Integer | 120 |
| Intruction_Set_Name | Instruction set block name |
String |
"Instruction_Set" |
| Dispatch_per_Cycle | maximum number of dispatch per cycle |
Integer | 10 |
| Power_Manager_Name | Name of the power table, this will enable the power observation of this block with required configuration in power table. "none" will diable the power feature |
String | "Manager_1" |
| Debug_Enable |
Used for internal debugging |
Boolean |
false |
| Port | Explanation |
| input |
This
port connects this block to the Rename stage. |
| to_Rename | This port connects this block to the Rename stage. |
| to_Exec | This port connects this block to the Execution stage. |
| Flow_Control |
This port connects this block to the Execution stage. |