Custom Hardware Routing

Parent Previous Next

Scenarios


Custom Hardware Routing Definitions

In this model, we disable the hello message generation by hardware accurate blocks such as Processor, Cache, DRAM and bus. We manually construct the routing table in the ArchitectureSetup block.

For this scenario, we use the previous model.

VisualSim model for the tutorial can be found in tje following location
$VS\doc\Training_Material\Tutorial\WebHelp\Tutorial\Architecture_Exploration\Processor_Modeling_Tutorial\Processor_Modeling_Part1_CustomRouting.xml

(Note: Purpose of this section is to enable designers to define the connectivity details between multiple blocks if custom hardware components are constructed using basic building blocks of VisualSim)


Modifying the existing task generator model





/* First row contains Column Names.                */
Source_Node    Destination_Node   Hop           Source_Port ;
Processor_1    L2_Cache           Port_Name_1   bus_out     ;
Processor_2    L2_Cache           Port_Name_1   bus_out     ;
L2_Cache       DRAM                 Port_Name_4   output      ;
DRAM           Processor_1         Port_Name_1   output      ;
DRAM           Processor_2         Port_Name_3   output      ;
Port_Name_1    L2_Cache         Port_Name_2   output2     ;
Port_Name_2    DRAM               Port_Name_4   output2     ;
Port_Name_3    L2_Cache         Port_Name_2   output2     ;
Port_Name_4    Processor_1      Port_Name_1   output1     ;
Port_Name_4    Processor_2      Port_Name_3   output1     ;    

Column Hop, corresponds to Bus Interface as Bus interface block acts as a Hop component between Processor and Memories. Port_Name_corresponds to Bus_Interface channel names that connects the two components.

AEA Routing Table
Figure 1: Routing Table

Statistics and Reports

Simulation reports for this section must be exactly same as the previous section with Hello Messages enabled.