Dual Processor Design - Part 1

VisualSim Tutorials ›› Dual Processor Design - Part 1 ››

Learning Objectives

Use the framework available in VisualSim to explore the architecture of a multi-core processor system for the following objectives:

Explore the system platform in a detailed and accurate fashion.
Size the individual components.
Distribute tasks on to a multicore platform.
Analyze the platform architecture by looking at performance statistics of Bus, Processor, and DRAM.

Design Methodology

We consider a system comprising a single core/dual core processor. A traffic generator sends application specific transactions to a target processor. In addition, we consider a main memory across a shared bus.

Two block diagrams depicting the system using a single as well as dual core processor are show below.

Figure 1: Single Core Block Diagram

Figure 2: Dual Core Block Diagram

VisualSim Model

VisualSim Models for this tutorial is available in the following location
$VS\doc\Training_Material\Tutorial\WebHelp\Tutorial\Architecture_Exploration\Processor_Modeling_Tutorial\Processor_Modeling_Part1.xml
$VS\doc\Training_Material\Tutorial\WebHelp\Tutorial\Architecture_Exploration\Processor_Modeling_Tutorial\Processor_Modeling_Part1_TaskGen.xml

Refer Fig 3 (Singe Core) and Fig 4 (Dual Core) for the intended VisualSim model.

Figure 3: Single Core VisualSim Model

Dual Core VisualSim Model
Figure 4: Dual Core VisualSim Model

Building the VisualSim Model

Assumptions

The procedures outlined below makes the following assumptions:

The user is aware of the process of connecting the blocks.
Lines and rectangles in red color within screenshots are used to indicate the block that is being built. These are not part of the VisualSim Modelling tool.
To assign a customized name to a parameter or a block, right-click the block and select Customize Name. In the resulting window, enter the Name.

Blocks Used

The following table list the blocks to be used in this model.

S.No.	Library Block	Description
1	Digital Simulator	The Digital Simulator implements the discrete-event Model of Computation (MoC). The simulator maintains a notion of current time, and processes events chronologically in this time. Used to model elements that change with time such as hardware, software and networks. Click here for detailed description and examples.
2	Traffic	Outputs a new Data Structure (DS) at time intervals specified by the "Time_Distribution" setting. A Data Structure is also knowns as a transaction and contains a list of Field Names + Values. Click here for detailed description and examples.
3	InstructionSet	Creates instruction references for the processor. Click here for further details.
4	ExpressionList	Executes a sequence of expressions in order. The default block contains one input and one output. The user can add multiple input and output ports. Click here for detailed description and examples.
5	Processor	Models variations of commercial and proprietary processors. Gets accurate timing, data flow, throughput, and power consumption of the processor.
6	Dynamic Mapper	Enables the mapping of behavior, task, or function on a target processor. Click here for further details.
7	Text_Display	Displays the values arriving on the input port in a text display dialog. Click here for detailed description and examples.
8	TimeDataPlotter	Plots the incoming data on the Y-Axis against the current simulation time on the X-axis. Every wire connected to this block input is considered a separate dataset and plotted separately. Click here for detailed description and examples.
9	BusArbiter	The Bus Arbiter block is the Arbiter for a Bus Interface. Click here for further details.
10	BusInterface	Connects devices to the BusArbiter and has a queue for each port. Click here for further details.
11	RAM	Combines the operation of a basic memory controller (delay function) and the memory array. Handles pre-fetch, read, write, refresh, and controller operations. Click here for further details.
12	ArchitectureSetup	Handles all the address mapping, routing, plotting, statistics, and debugging for the hardware modeling components. Click here for further details.
13	Cache	Emulates a cache in an architectural model. There are interfaces on both side of the block for connectivity. Click here for further details.
14	ResourceStatistics	Outputs or resets the statistics for all the SystemResource, Channel, Channel_N, Server, and Queues in the model. Click here for further details.
15	Timing Diagram	Enables the user to view a Gantt chart of the activity associated with the main architecture devices. Click here for further details.
16	Task Generator	Generates new tasks to execute on the processor. The mix of instructions in the task is read from the file that is referenced by the parameter Read_My_Instruction_Mix_Table. Click here for further details.

Scenarios

We consider the following two scenarios while building this model.

Build a generic scenario.

Consider very simple instruction sequence with a combination of multiple mnemonics corresponding to the selected processor.

Replace Task Instruction Sequence with Task Generator.

We replace the simple instruction sequence with a more accurate instruction sequence generated using Synthetic Instruction Generator in VisualSim.

Generic Scenario

Initial Setup

In the initial setup, you set the model parameters, drag and drop a Digital Simulator, and define an Instruction Set for the processors.

Create a new block diagram.

Define the following parameters from Model Setup > Parameter=.

Sim_Time: 100.0e-3

Sets the value for the simulation time and cannot be modified during a simulation. The Digital Simulator block uses this parameter.

Processor_Clock: 1000.0

Sets the clock speed of the processor and cannot be modified during a simulation. The Processor block uses this parameter.

Bus_Clock: 800.0

Sets the clock speed of the bus and cannot be modified during a simulation. The BusArbiter block uses this parameter.

L2_Cache_Clock: 800.0

Sets the clock speed of the cache and cannot be modified during simulation. The Cache block uses this parameter.

DRAM_Clock: 650.0

Sets the clock speed of the RAM and cannot be modified during simulation. The RAM block uses this parameter.

Figure 5: Parameters

Drag the DigitalSimulator block from Model Setup onto the block diagram.

Figure 6: Digital Simulator

Double click the DigitalSimulator and set the stopTime parameter as Sim_Time. The value is taken from the value that was set for Sim_Time in model parameters.

The rest of the parameters remain as default settings.

AEA Digital Simulator Parameters

Figure 7: Digital Simulator Parameters

- Drag and drop an InstructionSet from ProcessorGenerator to create instruction references for the Processor using a shorthand notation with indirect, user-defined naming references.

AEA Instruction Set
Figure 8: Instruction Set

Modify the Instruction_Set_Name parameter to “Instruction_Set”.
In the Instruction_Set_Text parameter, update the Mnemonics and Cycle delay for Integer Execution Unit and Floating Point Unit.
Update the other values of the Instruction_Set_Text parameter as given below.

/* Instruction Set or File Path. */
   Mnew Ra Rb Rc Rd   Re ;   /* Label */
   EXE IU FPU     ;
   IU   INT_1       ;
   FPU FP_1                ;

begin INT_1                 ;   /* Group */
   add 1                    ;
   mul 1                    ;
   div 2                    ;
   sub 1                    ;
end   INT_1                 ;

begin FP_1                  ;   /* Group */
   fadd 3                   ;
   fmul 3                   ;
   madd 3                   ;
   fdiv 17                  ;
   fsub 12                  ;
end   FP_1                  ;

Note that EXE is the Label that is associated with the different execution units in a processor. For example, Integer, Load/Store, Arithmetic, floating etc. In this case, we have two execution units namely IU and FPU representing Integer and Floating Point execution units and each has a group of mnemonics with cycle delay associated with the mnemonic.

AEA InstructionSet Parameters

Figure 9: Instruction Set Parameters

Architectural Elements

In this stage, you configure blocks to represent the architectural elements - Processors, Bus, Cache, and RAM.

Note: We consider a dual core processor for this tutorial. The procedures for a single core processor remain the same and you use only a single processor block.

Drag and drop the Processor block from ProcessorGenerator.

Figure 10: Processor 1

In the Processor block, set Processor_Name as “Processor_1”.
Use Processor_Setup to set the other parameters. The details are given below.

/* First row contains Column Names.                */
Parameter_Name                   Parameter_Value    ;
Processor_Instruction_Set:       Instruction_Set   ;
Number_of_Registers:             32                 ;
Processor_Speed_Mhz:             Processor_Clock    ;
Context_Switch_Cycles:           100                ;
Instruction_Queue_Length:        6                  ;
Number_of_Pipeline_Stages:       4                 ;
Number_of_INT_Execution_Units:   1                 ;
Number_of_FP_Execution_Units:    1                ;
Number_of_Cache_Execution_Units: 2                ;
I_1:            {Cache_Speed_Mhz=Processor_Clock, Size_KBytes=16.0, Words_per_Cache_Line=16, Cache_Miss_Name=L2_Cache}
D_1:            {Cache_Speed_Mhz= Processor_Clock, Size_KBytes=16.0, Words_per_Cache_Line=16, Cache_Miss_Name=L2_Cache}

Note that Processor_Instruction_Set is set to use the Instruction_Set and Processor_Speed_Mhz, I_1 cache and D_1 Cache uses the value for Processor_Clock set in the model parameters.

In Pipeline_Stages, enter the values as given below. Here we have a 4 stage pipeline.

/* First row contains Column Names.                */
Stage_Name   Execution_Location Action Condition ;
1_PREFETCH   I_1                 instr   none      ;
1_PREFETCH   D_1                 read    none      ;
2_DECODE     I_1                 wait    none      ;
3_EXECUTE    D_1                 wait    none      ;
3_EXECUTE    EXE                 exec    none      ;
4_STORE      EXE                 wait    none      ;
4_STORE      D_1                 write   none      ;

The rest of the parameters retain the default settings.

Figure 11: Processor 1 Parameters

Add one more processor block and set its Processor_Name parameter as Processor_2.

Note: In VisualSim, no two blocks can have the same name.

Configure the parameters of Processor_2 with the same details as that of Processor_1.

Add a BusArbiter from HardwareDevices.

The BusArbiter acts as a communication channel between master and slave devices. BusArbiter grants bus control to master devices based on the arbitration algorithm selected. The block can be configured to support First Come First Serve, Round Robin, and Custom arbitrations. In this tutorial, we will be considering First Come First Serve.

BusArbiter works in conjunction with BusInterface block. Bus Interface defines the physical connection with the devices; whereas Bus Arbiter controls the Bus Interface based on the selected arbitration.

Figure 12: Bus Arbiter

In the BusArbiter block, set the Bus_Speed_Mhz as Bus_Clock. Note that this value was set as part of the model parameters.

The rest of the parameters retain the default settings.

Figure 13: Bus Arbiter Parameter

Add two BusInterfaces from HardwareDevices.

The BusInterface receives data traffic and sends data traffic out on the Bus Arbiter. The block co-ordinates data transfer by handling control to the Linear Controller.

Figure 14: Bus Interface

In the second BusInterface, change the Port_Name_1 parameter to “Port_Name_3” and the Port_Name_2 parameter to “Port_Name_4” as the BusInterface must carry unique names.

The rest of the parameters retain the default settings. The first BusInterface retains all the default parameter settings.

Figure 15: Bus Interface 2 Parameters

Connect Top port of the top BusInterface to the bottom port of BusArbiter.

AEA Bus Arbiter Bus Interface Connection

Figure 16: Bus Arbiter - Bus Interface Connection

Connect the top port of the bottom BusInterface to bottom port of the top BusInterface.

AEA Bus Interface Bus Interface Connection

Figure 17: Bus Interface - Bus Interface Connection

Add a Cache block from ProcessorGenerator.

Figure 18: Cache

In the Cache block, set Cache_Name to “L2_Cache” to match the settings in the Processor block for I_1 Cache_Miss_Name.

The Cache acts as an external shared cache. If there is a I_1 or D_1 cache miss, then the Processor tries to get the instruction or data from the L2 cache.

Set the Miss_Memory_Name as “DRAM”. If there is L2 miss, then the data is accessed from DRAM. In this model, we have considered that L2 cache can have 95% hit.

Set the Cache_Speed_Mhz to L2_Cache_Clock. Note that this value was set as part of the initial parameters.

The rest of the parameters retain the default settings.

Figure 19: Cache Parameters

Add a RAM block from Memory.

Figure 20: RAM

In the RAM block, set the

Memory_Name to “DRAM”.
Memory_Speed_Mhz to DRAM_Clock. Note that this value was set as part of the initial parameters.
Access_Time to "Read 1000.0/Memory_Speed_Mhz, Prefetch 1000.0/Memory_Speed_Mhz, Write 1000.0/Memory_Speed_Mhz, ReadWrite 1000.0/Memory_Speed_Mhz, Erase 1000.0/Memory_Speed_Mhz".

Here we are setting the access time for Read, Write, Prefetch and Erase. The values are considered as nano seconds.

Memory_Type to DDR.

The rest of the parameters retain the default settings.

Figure 21: RAM Parameters

Connect the blocks.

Figure 22: RAM Connection

Architecture Setup

Add Architecture Setup from Hardware_Setup.

Architecture_Setup block handles all the address mapping, routing, plotting, statistics and debugging for the Hardware Modeling components. The architecture setup block configures the complete set of blocks linked to a single Architecture_Name parameter found in most blocks. There can be multiple Architecture_Setup blocks in a model. Each block instance must have a unique name. All Bus and Hardware blocks must be associated with one of the Architecture_Setup.

Figure 23: Architecture Setup

Processor, Bus, and DRAM blocks requires at least data structure fields such as A_Destination, A_Hop, A_IDX, A_Task_ID, and so on. These fields are predefined in Processor_DS, the datastructure file that is used while working with cycle accurate library blocks.

The Default Routing_Tabe parameter appears as follows. If the user constructs models only using Hardware Accurate library blocks such as Processor, Cache, DRAM, DeviceInterface, Bus and so on, then Routing_Table entries will not be considered as Hello Messages generated by these blocks will define the routing information.

/* First row contains Column Names.                */
Source_Node    Destination_Node   Hop           Source_Port ;
Processor_1    Cache_1            Port_1        bus_out2    ;
Cache_1        Processor_1        Port_2        output      ;
Cache_1        SDRAM_1            Port_2        output      ;
SDRAM_1        Cache_1            Port_4        output      ;
SDRAM_1        Processor_1        Port_4        output      ;

Note that checking Enable_Hello Messages means that every block within the hardware architecture library sends out Hello messages at simulation time 0.0 to determine the node-to-node connectivity. Each bus in the topology creates an internal routing table, based on the hello messages received, meaning the bus knows each end node it is connected to, and the user is freed from having to construct each bus routing table.

Hello Messages received by each to/from node are added to the routing table with the source, destination, port information. User entries to the routing table supplement the Hello message entries to simplify routing table construction.

Later in the Custom Hardware Routing definitions scenario, we disable the Hello Messages and manually construct a routing table.

Behavior Flow

In this tutorial, we consider a simple behavior sequence for a task, "My_Task_1". The task is generated every 1 ms. The task definitions such as the instructions and target processor details are updated using the Expression List block.

As we have two processor cores, 50% of the simulation time tasks are mapped on to Processor_1 and the remaining 50% of the time task is mapped on to Processor_2. Software task mapping is done with the help of Dynamic Mapper blocks available in VisualSim.

The step by step explanations are given below.

Drag and drop a Traffic block from Traffic.

Figure 24: Traffic

Update the Data_Structure_Name to “Processor_DS”.
Change Value_1 to 1.0e-3.
Set Time_Distribution to Fixed (Vaue_1).

The rest of the parameters retain the default settings.

Figure 25: Traffic Parameters

Add an ExpressionList from Behavior to assign the task to a relevant processor.

Figure 26: Expression List 1

Rename the ExpressionList block to SelectProcessor. (Note: Not a mandatory procedure).

Use the Expression_List parameter to add the following fields to the datastructure and also assign values.

RandNum = irand(0,100)

Generate random numbers to assist in the selection of processors.

input.A_Destination = (RandNum >= 50)?"Processor_1":"Processor_2"

Use random numbers to select a processor.

input.A_Hop = input.A_Destination

We consider that 50% of the time the tasks run on Processor_1 and remaining 50% on Processor_2.

It is important that we provide the correct name to A_Destination and A_Hop. If we provide the wrong name, then the task does not get mapped to the target platform and is rejected.

The rest of the parameters retain the default settings.

Figure 27: Expression List 1 Parameters

Add another ExpressionList block and rename it as TaskInstructionSequence.

In this step, we consider a simple instruction sequence. But it will be replaced by a synthetic instruction generator to generate more accurate instruction sequence for the task.

Use the ExpressionList parameter to add the following field to the datastructure. This field sets the list of instructions.

input.A_Instruction = {"add","mul","div","sub","fadd","fmul","fdiv","fsub"}

Update the other parameters as given below.

Output_Ports: output,output1
Output_Values: input,input
Output_Conditions: input.A_Destination == "Processor_1",input.A_Destination == "Processor_2"

Figure 28: Expression List 2

Right-click TaskInstruction Sequence and select Customize > Ports > Add to add another output port called output1.
Drag and drop two DynamicMapper blocks from Mappers.

The DynamicMapper block accepts a data structure on the input and sends this along with the information in block parameters to the target resource (Processor_1 or Processor_2).

Figure 29: Dynamic Mappers

In the DynamicMapper blocks, update the parameters with the following details.

Parameter	DynamicMapper	DynamicMapper2
Block_Name	Task_Mapper_1	Task_Mapper_2
Database_Lookup	none	none
Database_Expression	none	none
Task_Name	A_Task_Name	A_Task_Name
Task_Destination	Architecture_1.Processor_1	Architecture_1.Processor_2
Task_Instruction	A_Instruction	A_Instruction
Task_ID	1	1
Task_Plot_ID	1	1
Task_Priority	1	1
Task_Time	none	none

Figure 30: Dynamic Mapper 1 Parameters

Figure 31: Dynamic Mapper 2 Parameters

Resource Statistics and Reports

Statistics and Reports Generation

Attach an ExpressionList blocks to the DynamicMapper and DynamicMapper2 to capture the latency and MIPS.

Figure 32: Expression List

In the ExpressionList blocks, use the Expression_List parameter to add the following field to the datastructure. The field assists in outputting the latency details.

latency=TNow-input.TIME

Update the other parameters with the following details:

Output_Ports: output,mips
Output_Values: latency, input.MIPS_IN_PROCESSOR
Output_Conditions: true,true

Figure 33: Expression List Parameter

Right-click ExpressionList blocks and select Customize > Ports > Add to add another output port called mips.
Attach two TimeDataPlotter blocks from Results to the ExpressionList blocks.

Figure 34: TimeDataPlotters

In the TimeDataPlotter blocks, enter Processor_1, Processor_2 for legend.

The other parameters retain the default settings.

Figure 35: TimeDataPlotter Parameters

Capture a sample stats for Architecture Elements by connecting a Text Display from Results to Internal_Stats_Out port of Architecture Setup block.
Capture Utilization stats by connecting the text display to Util_Stats_Out port of Architecture Setup block.

Figure 36: Text Display

Add a TimingDiagram block from Hardware Setup.

Figure 37: Timing Diagram

Update the parameters of TimingDiagram block to match the names of the blocks. (Note: Each Processor block requires dedicated TimingDiagram block)

Statistics and Reports

Find below the screenshots of the reports.

Figure 38: Processor Unit Execution Activity

Figure 39: Latency Plot

Figure 40: MIPS Plot

DISPLAY AT TIME         ------ 100.0000000000 ms ------
{BLOCK                = ".Processor_Modeling_Part1.ArchitectureSetup",
Bus_1_Delay_Max            = 2.6154000007383E-8,
Bus_1_Delay_Mean        = 2.1950571428453E-8,
Bus_1_Delay_Min            = 2.1249999995754E-8,
Bus_1_Delay_StDev        = 1.7160425282895E-9,
Bus_1_IOs_per_sec_Max        = 16000.0,
Bus_1_IOs_per_sec_Mean        = 16000.0,
Bus_1_IOs_per_sec_Min        = 16000.0,
Bus_1_IOs_per_sec_StDev        = 0.0,
Bus_1_Input_Buffer_Occupancy_in_Words_Max    = 31.0,
Bus_1_Input_Buffer_Occupancy_in_Words_Mean    = 8.6266840504129,
Bus_1_Input_Buffer_Occupancy_in_Words_Min    = 0.0,
Bus_1_Input_Buffer_Occupancy_in_Words_StDev    = 8.0148255065604,
Bus_1_Preempt_Buffer_Occupancy_in_Words_Max    = 0.0,
Bus_1_Preempt_Buffer_Occupancy_in_Words_Mean    = 0.0,
Bus_1_Preempt_Buffer_Occupancy_in_Words_Min    = 0.0,
Bus_1_Preempt_Buffer_Occupancy_in_Words_StDev    = 0.0,
Bus_1_Throughput_MBs_Max    = 0.448,
Bus_1_Throughput_MBs_Mean    = 0.448,
Bus_1_Throughput_MBs_Min    = 0.448,
Bus_1_Throughput_MBs_StDev    = 0.0,
DELTA                = 0.0,
DRAM_Delay_Time_Max        = 2.3076923076923E-8,
DRAM_Delay_Time_Mean        = 1.3076923076923E-8,
DRAM_Delay_Time_Min        = 3.0769230769231E-9,
DRAM_Delay_Time_StDev        = 1.0E-8,
DRAM_Memory_Used_By_Processor_1_MB_Max    = 0.003712,
DRAM_Memory_Used_By_Processor_1_MB_Mean    = 0.003264,
DRAM_Memory_Used_By_Processor_1_MB_Min    = 0.002816,
DRAM_Memory_Used_By_Processor_1_MB_StDev    = 4.48E-4,
DRAM_Memory_Used_By_Processor_2_MB_Max    = 0.003584,
DRAM_Memory_Used_By_Processor_2_MB_Mean    = 0.003136,
DRAM_Memory_Used_By_Processor_2_MB_Min    = 0.002688,
DRAM_Memory_Used_By_Processor_2_MB_StDev    = 4.48E-4,
DRAM_Memory_Used_By_Total_MB_Max    = 0.0064,
DRAM_Memory_Used_By_Total_MB_Mean    = 0.0064,
DRAM_Memory_Used_By_Total_MB_Min    = 0.0064,
DRAM_Memory_Used_By_Total_MB_StDev    = 0.0,
DRAM_Throughput_MBs_Max        = 0.128,
DRAM_Throughput_MBs_Mean    = 0.128,
DRAM_Throughput_MBs_Min        = 0.128,
DRAM_Throughput_MBs_StDev    = 0.0,
DS_NAME                = "Architecture_Stats",
ID                = 2,
INDEX                = 0,
L2_Cache_Delay_Time_Max        = 2.0E-8,
L2_Cache_Delay_Time_Mean    = 1.4642857142857E-8,
L2_Cache_Delay_Time_Min        = 1.25E-9,
L2_Cache_Delay_Time_StDev    = 8.470386589737E-9,
L2_Cache_Hit_Ratio_Max        = 98.0,
L2_Cache_Hit_Ratio_Mean        = 97.7142857142857,
L2_Cache_Hit_Ratio_Min        = 97.4285714285714,
L2_Cache_Hit_Ratio_StDev    = 0.2857142857127,
L2_Cache_Memory_Used_By_DRAM_MB_Max    = 0.0064,
L2_Cache_Memory_Used_By_DRAM_MB_Mean    = 0.0064,
L2_Cache_Memory_Used_By_DRAM_MB_Min    = 0.0064,
L2_Cache_Memory_Used_By_DRAM_MB_StDev    = 0.0,
L2_Cache_Memory_Used_By_Processor_1_MB_Max    = 0.00928,
L2_Cache_Memory_Used_By_Processor_1_MB_Mean    = 0.00816,
L2_Cache_Memory_Used_By_Processor_1_MB_Min    = 0.00704,
L2_Cache_Memory_Used_By_Processor_1_MB_StDev    = 0.00112,
L2_Cache_Memory_Used_By_Processor_2_MB_Max    = 0.00896,
L2_Cache_Memory_Used_By_Processor_2_MB_Mean    = 0.00784,

L2_Cache_Memory_Used_By_Processor_2_MB_Min    = 0.00672,
L2_Cache_Memory_Used_By_Processor_2_MB_StDev    = 0.00112,
L2_Cache_Memory_Used_By_Total_MB_Max    = 0.0224,
L2_Cache_Memory_Used_By_Total_MB_Mean    = 0.0224,
L2_Cache_Memory_Used_By_Total_MB_Min    = 0.0224,
L2_Cache_Memory_Used_By_Total_MB_StDev    = 0.0,
L2_Cache_Throughput_MBs_Max    = 0.328,
L2_Cache_Throughput_MBs_Mean    = 0.328,
L2_Cache_Throughput_MBs_Min    = 0.328,
L2_Cache_Throughput_MBs_StDev    = 0.0,
Processor_1_Context_Switch_Time_Pct_Max    = 0.005858,
Processor_1_Context_Switch_Time_Pct_Mean    = 0.005151,
Processor_1_Context_Switch_Time_Pct_Min    = 0.004444,
Processor_1_Context_Switch_Time_Pct_StDev    = 7.07E-4,
Processor_1_D_1_Hit_Ratio_Max    = 0.0,
Processor_1_D_1_Hit_Ratio_Mean    = 0.0,
Processor_1_D_1_Hit_Ratio_Min    = 0.0,
Processor_1_D_1_Hit_Ratio_StDev    = 0.0,
Processor_1_D_1_KB_per_Thread_Max    = 0.0,
Processor_1_D_1_KB_per_Thread_Mean    = 0.0,
Processor_1_D_1_KB_per_Thread_Min    = 0.0,
Processor_1_D_1_KB_per_Thread_StDev    = 0.0,
Processor_1_I_1_Hit_Ratio_Max    = 100.0,
Processor_1_I_1_Hit_Ratio_Mean    = 44.4444444444444,
Processor_1_I_1_Hit_Ratio_Min    = 0.0,
Processor_1_I_1_Hit_Ratio_StDev    = 49.6903994999953,
Processor_1_I_1_KB_per_Thread_Max    = 0.0,
Processor_1_I_1_KB_per_Thread_Mean    = 0.0,
Processor_1_I_1_KB_per_Thread_Min    = 0.0,
Processor_1_I_1_KB_per_Thread_StDev    = 0.0,
Processor_1_Stall_Time_Pct_Max    = 0.001856,
Processor_1_Stall_Time_Pct_Mean    = 0.001632,
Processor_1_Stall_Time_Pct_Min    = 0.001408,
Processor_1_Stall_Time_Pct_StDev    = 2.24E-4,
Processor_1_Task_Delay_Max    = 1.4499900000131E-7,
Processor_1_Task_Delay_Mean    = 1.1955455555611E-7,
Processor_1_Task_Delay_Min    = 1.0499899999461E-7,
Processor_1_Task_Delay_StDev    = 1.5341382750109E-8,
Processor_2_Context_Switch_Time_Pct_Max    = 0.005656,
Processor_2_Context_Switch_Time_Pct_Mean    = 0.004949,
Processor_2_Context_Switch_Time_Pct_Min    = 0.004242,
Processor_2_Context_Switch_Time_Pct_StDev    = 7.07E-4,
Processor_2_D_1_Hit_Ratio_Max    = 0.0,
Processor_2_D_1_Hit_Ratio_Mean    = 0.0,
Processor_2_D_1_Hit_Ratio_Min    = 0.0,
Processor_2_D_1_Hit_Ratio_StDev    = 0.0,
Processor_2_D_1_KB_per_Thread_Max    = 0.0,
Processor_2_D_1_KB_per_Thread_Mean    = 0.0,
Processor_2_D_1_KB_per_Thread_Min    = 0.0,
Processor_2_D_1_KB_per_Thread_StDev    = 0.0,
Processor_2_I_1_Hit_Ratio_Max    = 100.0,
Processor_2_I_1_Hit_Ratio_Mean    = 44.4444444444444,
Processor_2_I_1_Hit_Ratio_Min    = 0.0,
Processor_2_I_1_Hit_Ratio_StDev    = 49.6903994999953,
Processor_2_I_1_KB_per_Thread_Max    = 0.0,
Processor_2_I_1_KB_per_Thread_Mean    = 0.0,
Processor_2_I_1_KB_per_Thread_Min    = 0.0,
Processor_2_I_1_KB_per_Thread_StDev    = 0.0,
Processor_2_Stall_Time_Pct_Max    = 0.001792,
Processor_2_Stall_Time_Pct_Mean    = 0.001568,
Processor_2_Stall_Time_Pct_Min    = 0.001344,
Processor_2_Stall_Time_Pct_StDev    = 2.24E-4,
Processor_2_Task_Delay_Max    = 1.4499900000131E-7,
Processor_2_Task_Delay_Mean    = 1.1955455555573E-7,
Processor_2_Task_Delay_Min    = 1.0499899999461E-7,
Processor_2_Task_Delay_StDev    = 1.5341382750299E-8,
TIME                = 0.1}

Figure 41: Text Display

Note: The HW_DRAM_Bank and Bus Activity plot is not being displayed as we are not using HW_DRAM.

Replace Task Instruction Sequence with Task Generator

In this model, we replace the Task Instruction Sequence block with a Task Generator. The TaskGenerator block generates synthetic instructions for the target processor based on the user inputs on number of instructions and possible combination of instruction types such as arithmetic, logical, integer, load/store etc.

An image of the proposed model is given below.

Figure 42: VisualSim Model with Task Generator

Modifying the existing architecture exploration model

In the existing architecture exploration model, delete the TaskInstruction Sequence block.
Drag and drop a TaskGenerator block from ProcessGenerator.

Figure 43: Task Generator

Instruction sequence for each task is generated by reading an Instruction_Mix_Table. Sample Instruction Mix Table file that we are going to use in this tutorial is shown below.

Figure 44: Sample Instruction Table

Here, first part defines the instruction types and associated mnemonics and the second part defines the number of instructions for each task and combination of instruction types in percentage.

Create a text file as shown in figure above and save in the same directory where the model is being saved.

In the TaskGenerator block, modify the following parameters.

Instruction_Mix_Table: Select Instruction Mix Table file.

Figure 45: Task Generator Parameters

Add an ExpressionList block from Behavior to route the instructions to a relevant processor.

Figure 46: Task Generator Expression List

Rename the ExpressionList as WhichProcessor? (Note: Not mandatory)

Update the WhichProcessor block parameters as given below.

Expression_List: Leave it blank.
Output_Ports: output,output1
Output_Values: input,input
Output_Conditions: input.A_Destination == "Processor_1",input.A_Destination == "Processor_2"

AEA Task Generator Expression List Parameters

Figure 47: Task Generator Expression List Parameters

Add another output port to the WhichProcessor block.
Connect the blocks.

Figure 48: Task Generator Model

Statistics and Reports

Find below the screenshots of the reports.

Figure 49: Task Generator Processor Execution Unit Activity

Figure 50: Task Generator Latency

Figure 51: Task Generator MIPS

DISPLAY AT TIME         ------ 100.0000000000 ms ------
{
Processor_1_Context_Switch_Time_Pct_Max    = 0.004848,
Processor_1_Context_Switch_Time_Pct_Mean    = 0.004848,
Processor_1_Context_Switch_Time_Pct_Min    = 0.004848,
Processor_1_Context_Switch_Time_Pct_StDev    = 0.0,
Processor_1_D_1_Hit_Ratio_Max    = 0.0,
Processor_1_D_1_Hit_Ratio_Mean    = 0.0,
Processor_1_D_1_Hit_Ratio_Min    = 0.0,
Processor_1_D_1_Hit_Ratio_StDev    = 0.0,
Processor_1_D_1_KB_per_Thread_Max    = 0.0,
Processor_1_D_1_KB_per_Thread_Mean    = 0.0,
Processor_1_D_1_KB_per_Thread_Min    = 0.0,
Processor_1_D_1_KB_per_Thread_StDev    = 0.0,
Processor_1_I_1_Hit_Ratio_Max    = 100.0,
Processor_1_I_1_Hit_Ratio_Mean    = 80.0355859590934,
Processor_1_I_1_Hit_Ratio_Min    = 0.0,
Processor_1_I_1_Hit_Ratio_StDev    = 39.7193069184094,
Processor_1_I_1_KB_per_Thread_Max    = 0.0,
Processor_1_I_1_KB_per_Thread_Mean    = 0.0,
Processor_1_I_1_KB_per_Thread_Min    = 0.0,
Processor_1_I_1_KB_per_Thread_StDev    = 0.0,
Processor_1_Stall_Time_Pct_Max    = 0.011006,
Processor_1_Stall_Time_Pct_Mean    = 0.010885,
Processor_1_Stall_Time_Pct_Min    = 0.010764,
Processor_1_Stall_Time_Pct_StDev    = 1.2100000000002E-4,
Processor_1_Task_Delay_Max    = 5.7299900000155E-7,
Processor_1_Task_Delay_Mean    = 3.2370287645205E-7,
Processor_1_Task_Delay_Min    = 1.0499899999461E-7,
Processor_1_Task_Delay_StDev    = 1.2443263817956E-7,
Processor_2_Context_Switch_Time_Pct_Max    = 0.005252,
Processor_2_Context_Switch_Time_Pct_Mean    = 0.005252,
Processor_2_Context_Switch_Time_Pct_Min    = 0.005252,
Processor_2_Context_Switch_Time_Pct_StDev    = 0.0,

Processor_2_D_1_Hit_Ratio_Max    = 0.0,
Processor_2_D_1_Hit_Ratio_Mean    = 0.0,
Processor_2_D_1_Hit_Ratio_Min    = 0.0,
Processor_2_D_1_Hit_Ratio_StDev    = 0.0,
Processor_2_D_1_KB_per_Thread_Max    = 0.0,
Processor_2_D_1_KB_per_Thread_Mean    = 0.0,
Processor_2_D_1_KB_per_Thread_Min    = 0.0,
Processor_2_D_1_KB_per_Thread_StDev    = 0.0,
Processor_2_I_1_Hit_Ratio_Max    = 100.0,
Processor_2_I_1_Hit_Ratio_Mean    = 80.166475315729,
Processor_2_I_1_Hit_Ratio_Min    = 0.0,
Processor_2_I_1_Hit_Ratio_StDev    = 39.6057602585533,
Processor_2_I_1_KB_per_Thread_Max    = 0.0,
Processor_2_I_1_KB_per_Thread_Mean    = 0.0,
Processor_2_I_1_KB_per_Thread_Min    = 0.0,
Processor_2_I_1_KB_per_Thread_StDev    = 0.0,
Processor_2_Stall_Time_Pct_Max    = 0.011776,
Processor_2_Stall_Time_Pct_Mean    = 0.01169,
Processor_2_Stall_Time_Pct_Min    = 0.011604,
Processor_2_Stall_Time_Pct_StDev    = 8.6000000000108E-5,
Processor_2_Task_Delay_Max    = 5.7299900000501E-7,
Processor_2_Task_Delay_Mean    = 3.2205382204324E-7,
Processor_2_Task_Delay_Min    = 1.0499899999461E-7,
Processor_2_Task_Delay_StDev    = 1.2373799043996E-7,
TIME                = 0.1}

Figure 52: Task Generator Text Display (Full Stats is not displayed here)

System Analysis

With default configurations we noticed that the hardware architecture was hardly utilized and hence modified system configurations to understand system performance.

We have used the model parameters listed below to modify system configurations.

Processor_Clock = 100.0 /* MHz */
Bus_Clock = 80.0 /* MHz */
L2_Cache = 80.0 /* MHz */
DRAM_Clock = 65.0 /*MHz */

We also increased Traffic rate from 1 ms to 1 us.

We looked at the MIPS. MIPS for both the processors was below 2 MIPS majority of the times. The Processor utilization statistics suggested that the processors used only about 2.5% and Pipeline was utilized only about 4%.

Processor_1_PROC_Utilization_Pct_Max    = 2.64,
Processor_1_PROC_Utilization_Pct_Mean    = 2.64,
Processor_1_PROC_Utilization_Pct_Min    = 2.64,
Processor_1_PROC_Utilization_Pct_StDev    = 0.0,
Processor_1_Pipeline_Utilization_Pct_Max    = 4.54,
Processor_1_Pipeline_Utilization_Pct_Mean    = 4.54,
Processor_1_Pipeline_Utilization_Pct_Min    = 4.54,
Processor_1_Pipeline_Utilization_Pct_StDev    = 0.0,
Processor_1_Stall_Time_Pct_Max    = 14.53,
Processor_1_Stall_Time_Pct_Mean    = 14.53,
Processor_1_Stall_Time_Pct_Min    = 14.53,
Processor_2_Stall_Time_Pct_Max    = 14.016,
Processor_2_Stall_Time_Pct_Mean    = 14.016,
Processor_2_Stall_Time_Pct_Min    = 14.016,

This suggests that the Processor is not occupied with processing majority of the times and is underutilized with a Stall time percentage of 14%.

If we look at the Stats for the Bus, Cache and RAM as shown below.

Bus_1_Utilization_Pct_Max    = 93.7274999999925,
Bus_1_Utilization_Pct_Mean    = 93.4062499999925,
Bus_1_Utilization_Pct_Min    = 93.0849999999926,
Bus_1_Utilization_Pct_StDev    = 0.321249999998,
DRAM_Utilization_Pct_Max    = 47.1076923076937,
DRAM_Utilization_Pct_Mean    = 46.8430769230783,
DRAM_Utilization_Pct_Min    = 46.5784615384629,
DRAM_Utilization_Pct_StDev    = 0.2646153846157,
L2_Cache_Utilization_Pct_Max    = 80.4875000000015,
L2_Cache_Utilization_Pct_Mean    = 79.0325000000015,
L2_Cache_Utilization_Pct_Min    = 77.5775000000015,
L2_Cache_Utilization_Pct_StDev    = 1.4549999999998,

Bus and L2 Cache are extremely busy with over 70% utilization and tells us that these could be the bottleneck if we increase the workload.

Processor_1_I_1_Hit_Ratio_Max    = 100.0,
Processor_1_I_1_Hit_Ratio_Mean    = 44.4709772226304,
Processor_1_I_1_Hit_Ratio_Min    = 0.0,
Processor_1_I_1_Hit_Ratio_StDev    = 49.6887380194589,
Processor_2_I_1_Hit_Ratio_Max    = 100.0,
Processor_2_I_1_Hit_Ratio_Mean    = 44.4444444444444,
Processor_2_I_1_Hit_Ratio_Min    = 0.0,
Processor_2_I_1_Hit_Ratio_StDev    = 49.6903994999953,

We also noticed that I Cache hit rate is only about 44% most of the time and suggests that Processor pipeline is waiting for the instructions and pushes for the stall time of nearly 14%.

This suggests that we must increase the I_1 Cache size or have an on chip dedicated L2 Cache to improve the performance.

As part of continued analysis, we recommend users to modify the system parameters and workload scenarios and analyze the reports collected.