Cycle Accurate A77 Processor Design 

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Contents

         Building Blocks

          Placement and Connection

                  Standard Library Blocks

                  Cycle Accurate Library Blocks

                  Memory Library blocks

                  Interconnect Library blocks

                 Miscellaneous Library blocks          

          Key Configurations

                 Required Parameters

                 Required Variables

                 Instruction Feed configuration

                 Instruction Set configuration                 

                 Power Table configuration          

          Code Implementation

          Analysis

Building Blocks                                                       Library Location

   1. Digital Simulator                                                     Model Setup              => DigitalSimulator
   2. Architecture Setup                                                  Hardware Setup        => ArchitectureSetup
   3. Instruction Set                                                        ProcessorGenerator  => Instruction_Set
   4. Power Table (Optional)                                           Power                      => PowerTable
   5. Cycle Accurate Processor Block set                        Cycle_Accurate_Processor
   6. Integrated cache                                                    Memory                    => Integrated_Cache
   7. TLB                                                                       Memory                    => TLB
   8. Bus Arbiter and Bus Interface                                  HardwareDevices      => BusArbiter, BusInterface
   9. AXI Bus                                                                 Interfaces and Buses => AMBA => AMBA_AXI
   10. Memory controller and CycleAccurateDRAM          Memory                    => Memory_Controller, CycleAccurateDRAM
   11. Database                                                             File IO                      => Database
   12. Variable List                                                         Model Setup             => VariableList

Placement and Connection

        **Every block must have a unique name.

        Standard Library Blocks

            Place the following library blocks (drag and drop) in the block diagram editor.

       
                                      Blocks
                                   Configuration
Digital Simulator stopTIme = 10.0e-6
A top level parameter named Sim_Time can be defined and linked to this parameter
click here to see how to add a parameter in the model
Architecture Setup No additional configuration
Instruction Set Click here
Power Table (optional) Click here

        Cycle Accurate Library Blocks

            Place the Cycle Accurate processor blocks as below
                            Image not found in local directory
                  *for detailed documentation please check the "Library Documentation" from tool window(VisualSim Block Documentataion => Cycle Accurate Processor=>library list) or right click on the block to get documentation (Documentation =>Get Documentation)
                  **for web documentation please use the link in Google Chrome
      
             Blocks
                                       Connection
Branch Predictor
                                 File not found in local directory
Right side ports are connected to fetch stage or intermediate blocks between BPU and Fetch stage.
to_Fetch - Issues flow control request and Predicted address sequence to Fetch stage
Frm_Fetch - Flow control response

Bottom ports are connected from Decode stage and commit stage.
It is a feedback connection for branch table update.
Fetch Unit
                           Image not found in local directory
Left side ports are connected to Branch unit or the intermediate stage between Branch and fetch unit.
Frm_Branch - Flow control request and predicted address sequence input
to_Branch  - Flow control resposnse

Right side ports are connected to Decode Stage or intermediate stage between Fetch and Decode Unit
to_Decode    -  Issues flow control and fetched Instruction to Decode stage
Frm_Decode -   Flow control response

Bottom Ports are connected to L1 Instruction cache and MoP cache.
Instruction fetch requests to corresponding caches.
Decode Stage
                 Image not found in local directory
Left side ports are connected to Fetch unit or the intermediate stage between fetch and decode unit.
Decode_inp - Flow control request and fetched instruction input
to_Fetch  - Flow control resposnse

Right side ports are connected to MUX or Rename Stage or intermediate stage between Decode and Rename Unit
to_MUX    -  Issues decoded instructions to rename stage
Frm_MUX -   Flow control response

Bottom Port is connected to Branch Predictor
Feedback path for unconditional branch update
MUX
               Image not found in local directory
Left side ports are connected to Decode stage and MoP Cache
Frm_Decode - Decoded instruction input
to_Decode    - Flow control trigger

Right side ports are connected to Rename stage
MUX_out       -  Forwards the packets from Decode stage or MoP cache as per the control sequence
Frm_Rename -  Flow control response

Bottom Port is connected to MoP cache.
Decoded Instruction update to MoP cache.
MoP
            Image not found in local directory
Left side ports are connected to fetch unit.
Mop_inp   - Flow control request and fetch request from fetch unit
Mop_Resp - Flow control resposnse and Miss response to fetch unit

Right side ports are connected to MUX
Mop_Out    -  Issues decoded intructions to Rename stage through MUX
Frm_next_Stage -   Flow control response

Bottom Port is connected to MUX
Decoded instruction update.
Rename_Allocate_Stage
             Image not found in local directory
Left side ports are connected to Decode unit or intermediate blocks between decode and rename.
input - Decoded instruction input
to_Decode  - Flow control resposnse

Right side ports are connected to dispatch Stage or intermediate stage between Rename and Dispatch Unit
to_Dispatch    -  Issues flow control and Uops to dispatch stage
Frm_Dispatch -   Flow control response

Bottom Port
Frm_Commit - Conditional branch flush and Flow control trigger
ROB_Occupancy - ROB occupancy value throughout the simulation, can be connected to plotter.
Instruction fetch requests to corresponding caches.
Dispatch Stage
              File not found in local directory
Right side ports are connected to Execution stage or intermediate blocks between Dispatch and Execution unit.
to_Exec - Issues instructions that are ready to execute
Flow_Control - Flow control response

Right side ports are connected to Rename stage
input - Uops input
to_Rename  - Flow control resposnse
Execution_Unit
                     File not found in local directory
Left side ports are connected to Dispatch stage or intermediate blocks between Dispatch and Execution unit.
input - Instructions that needs to be executed
Flow_Control- Flow control response

Bottom ports are connected to Commit stage and D cache.
Output - Executed instruction output
to_D_Cache  - Memory access request from Load/Store unit
frm_D_Cache - Data response from D cache
Commit_Stage
                     Image not found in local directory
Left side port is connected to Brach unit
Conditional branch feedback

Right side port is connected from Execution Unit
Executed instruction input

Top Ports

to_Rename - Conditional branch flush and flow control trigger based on ROB availability
ROB_Occupancy  - ROB size thorughout the simulation (size after instruction commit)

Bottom Port is connected to L1 Data cache.
writeback to D cache.

        Memory Library blocks

              Place the Memory blocks as below
                                           Image not found in local directory
                  *for detailed documentation please check the "Library Documentation" from tool window(VisualSim Block Documentataion => Cycle Accurate Processor=>library list) or right click on the block to get documentation (Documentation =>Get Documentation)
                  **for web documentation please use the link in Google Chrome
                Blocks                                                 Connection
I and D cache
 Instantiation of class file:
Graph (from Tool bar) => Instantiate Class
enter class name as
   VisualSim.actor.arch.Processor_Blocks.I_Cache      - for I cache
   VisualSim.actor.arch.Processor_Blocks.D_Cache     - for D cache
                    Image n ot found in local directory  
I cache internal structure          D cache internal structure
Image not found in local directory              Image not found in local directory
TLB                            Image not found in local directory
input -  Virtual address input
output - Physical address output
Top ports connected to Page table at the last level TLB
L1 TLBs communicate virtually to L2 TLB
Integrated Cache                       Image not found in local directory
Left side ports - connected to Processor or lower level cache
Right side ports - connected to higher level cache or main memory for data fetch

VIPT_Addr_Check - connects to TLB in VIPT mode for parallel tag check

Bottom ports -  used for analysis Thoughput & latency can be connected to plotter and Debug can be connected to text display if debugging is enabled
Memory controller and DRAM
 Image not found in local directory

rd_wr_data_fm_bus - memory access request from cache
rd_data_wr_resp_to_bus - memory access response to cache
status - Debug port

        Interconnect Library blocks

                  
               Blocks
                                             Connection
                   Key Configuration
Bus Arbiter and Bus interface
                      Image not found in local directory

 Bus Name should be same in bus arbiter and multiple bus interface
which all represent the same bus.
Port name should be updated in each bus interface to be unique.
AXI bus
                            Image not found in local directory
for detailed configuration please refer the Block documentation.
Slave device name should be configured in the "Device_Attached_to_Slave_by_port" parameter.
Bus Width - according to the design
Read/Write threshold - according to the design
 

        Miscellaneous Library blocks

                  *for detailed documentation please check the "Library Documentation" from tool window(VisualSim Block Documentataion => Cycle Accurate Processor=>library list) or right click on the block to get documentation (Documentation =>Get Documentation)
                  **for web documentation please use the link in Google Chrome
                  Blocks
                            Libray Location
Parameter
to set unique name - (right click=> Customize Name)
 Model Setup => Parameter=
Database
FileorURL option will load the lookput table from a file
if it is not configured then the
FIle IO => Database
Variable List
 Model Setup => VariableList
Expression List
 Behavior => Expression List
Script
 Behavior => Script
Relation block (small rhombus shaped connector)
connects multiple blocks/wires		 Toolbar
Join/Fork
 Behavior => Join, Fork
Text Display
 Results => TextDisplay
TimeDataPlotter
 Results => TimeDataPlotter


Key Configurations

       Required Parameters


                           Top Level Parameter
                                           Description
Disassembly_File
 Disassembly file name
linked to a database block named "Instruction_Cache_Feed"
Sim_Time
(Optional- it can be configured directly in the block)
 Simulation time
linked to the digital simulato stopTime
Processor_Speed_Mhz
(Optional- it can be configured directly in the block)
 Core speed
linked to all the pipeline stages and necessary blocks
Uop_per_cycle
(Optional- it can be configured directly in the block)
 Number of UoP per cycle can be issue to dispatch stage
linked to Rename and commit stage
Dispatch_per_Cycle
(Optional- it can be configured directly in the block)
 Number of instructions that can be dispatched in a single cycle
linked to Dispatch unit
Page_Size
(Optional- it can be configured directly in the block)
 Page Size for TLB configuration
linked to all TLBs
VA_Start_Addr
(Optional- it can be configured directly in the block)
 Start of virtual address
linked to all TLBs
PA_Start_Addr
(Optional- it can be configured directly in the block)
 Start of Physical address
linked to all TLBs
Power_Enable
(Optional- it can be configured directly in the block)
 Enable or disable power feature
linked to all pipleine stages
Debug_Enable
(Optional- it can be configured directly in the block)
 Enable or disablel debug feature
linked to all pipeline stages

       Required Variables

                  Global variables are used to support the internal logic in each pipeline stages.
                /* Memory Initialize Template         
Name                  Type          Value     */
Mop_Cache_Arr            global        {}       ;  /* Mem1 */
Commit_Instr_Arr        global        {}       ;
Rename_Inst_Arr         global        {}       ;
Fetch_Stalls            global        false    ;
Exec_Stalls             global        false    ;
Count                   local         0        ;
ROB_Inst                global        {}       ;
ROB_ID                  global        {}       ;
ROB_TS                  global        {}       ;
MUX_Sel                 global        {}       ;
MUX_Addr                global        {}       ;
cnt                     global        0        ;
Initial_PC              global        0L       ;
Link_register_Val       global        {-1L}    ;
Decode_Flush            global        false    ;
Flush_Before            global        -1L      ;
Commit_Flush            global        false    ;
Prog_EXIT               global        false    ;

       Instruction Feed configuration

                   A database block should be placed in the design with the Linking name as "Instruction_Cache_Feed"
                   FileorURL must contains the disassambly trace file name. it can be linked to top level parameter or directly configured with the file name.
                   Input_Fields and Lookup_Fields must have the following field names - "Address,Instruction,Registers"
                   Database needs to be in "Read" mode

       Instruction Set configuration

                   Instruction set must have the list of instructions that the processor architecture supports. it also should have the corresponding cycle count and the execution unit which it belongs.
                   **Currently less number of instructions are specified, a detailed list of instructions and necessary detalis will be added in the form of a text file.
    /* Instruction Set or File Path. */
    Mnew Ra  Rb  Rc  Rd   Re  Rf Rg Rh        ; /* Label */
   ARM ALU BCH MDV LOD STO ;

   ALU  INT                      ; /*Simple Cluster 1*/
   BCH  FP                       ; /*Floating Point*/
   LDST LS                       ; /*Load store*/
  
begin INT                 ;
movz             I     1     ;
mov              I     1     ;
cmp             I     1     ;
cset             I     1     ;
nop             I     1     ;
movk           I     1     ;
orr              I     1     ;
eor             I     2     ;
add             I     1     ;
sub             I     1     ;
subs            I     1     ;
adrp            I     1     ;
b                B     1     ;
bl               B     1     ;
ret              B     1     ;
cbz             B     1     ;
cbnz           B     1     ;
ccmp          I     1     ;
b.eq            B     1     ;
b.ne            B     1     ;
b.ls             B     1     ;
b.cc            B     1     ;
b.hi             B     1     ;
and             I     1     ;
tbz              B     1     ;
tbnz            B     1     ;
mrs             I     1     ;
lslv              I     1     ;
ubfm           I     1     ;
csinc          I     1     ;
ands           M     2     ;
end INT                    ;

begin FP                 ;
fabs            V     2     ;
fadd            V     2     ;
fsub            V     2     ;
fccmp         V0    2     ;
fdiv             v0    7     ;
fneg            V     2     ;
fmov            V     2     ;
end FP                    ;

begin LS                       ;
ldr              L     4     ;
ldp             L     4     ;
ldrb            L     4     ;
stp             L     4     ;
str              L     1     ;
end LS                      ;

       Power Table configuration

             Power table contains the detailed states and corresponding power values for each block. Power feature for a block can be enabled by setting the power manager name in the specific block and the corresponding block details in the power table.
             if the power is enabled in the block but the power details are not furnished in the power table then an error will be thrown.
             Please check the "Power_Manager_Name" parameter in all the cycle accurate processor blocks, if it is none then the power will be disabled for that feature. To enable it the power manager name should be configured.
             Following are the reference names for power table configuration
Manager Setup:

--------Device Name-------           ---------Power States------  -----Operating States------  --toActive--  --Speed--  --Exist-- */
Architecture_Block                       Standby  Active  Wait  Idle Down Existing  OffState  OnState    t_OnOff        Mhz       Volts   ;
STR_Core_1_INT_Processing         stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
STR_Core_1_Branch_Processing    stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
STR_Core_1_MC_INT_Processing  stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
STR_Core_1_FP_Processing          stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
STR_Core_1_LS_Processing          stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Architecture_1_Bus_1                    stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Core_1_Branch_Predict                 stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Core_1_Fetch                               stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Core_1_Decode                            stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Core_1_MOP                                stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Core_1_Rename                           stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Core_1_Commit                            stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Cache_I1_Cache                           stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Cache_D1_Cache                          stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;
Cache_L2_Cache                          stdy     act     wat   idl   slp  Standby   Standby   Active     Cycle_t       Processor_Speed_Mhz     1.0     ;

Expressions:                                                                  
---------Reference--------          --------------Expression------------ */
Name                                             Value                   ;
Cycle_t                                            0                        ;
act                                                  38.0                    ;
stdy                                               0.1*act                 ;
wat                                               0.95*act                ;
idl                                                0.25*act                 ;
slp                                               0.02*act                 ;


            Average power and instantaneous power can be observed from the Right-top 2 ports of the power table.
            Power states throughout the simulation can be obtained in the Right bottom port of the power table.


       

Code Implementation

                Script code in each Blocks
                         Script code is classified into following sections
                                     1. Initialization of variables
                                     2. Input Handling
                                     3. Processing and Processing Delay
                                     4. Output handling

                           Variable initialization
                                     Variable of any type can be initialized with a unique name and the initial value
                                     eg:
                                              First_Pass       = true
                                              Sample_Count = 10
                                              Delta               = 0.0
                                              Str                  = "none"
                                              Matrix             = newArray(3,newArray(3,{}))

                            Input handling
                                     input packets can be enqueue in a queue and processed later according the logic.
                                     eg:
                                           QUEUE("Input_Q",port_token,1,"put")
                                           ......
                                           ......
                                           port_token           = QUEUE("Input_Q",pop)
                                                 
                                     If there are multiple input ports then current operation needs to find out which port it belongs.
                                     eg:
                                           if (port_name == "input"){
                                                 ......
                                           }
                                           else if(port_name == "input2"){
                                                 ......
                                           }
                                     In order to identify different packets( or flows) a common field with different values (or unique field) can be added.
                                     eg:
                                           if (port_token.check("Request_Grant")){
                                                    .....
                                            }
                                           else{
                                                    ......
                                            }
   
                                       or
                                            if(port_token.Flow_Name == "Flow1"){
                                                    ......
                                             }
                                             else if (port_token.Flow_Name == "Flow2"){
                                                    ......
                                             }
                                             else{
                                                    ......
                                             }

                            Processing
                                   All standard condition check, loops, switch, function call and jump logics can be implemented in the script code.
                                   *for detailed syntax please check the block documentation for script block.

                            Processing Delay
                                  Delay can be implemented in the following methods
                                  Blocked operation
                                              WAIT(Delta)       // Variable "Delta" must have the delay value
                                         this will block the entire block during that interval.
                                  Non Blocked Operation
                                              TIMEQ("Processing1",port_token,0,Delta)       // Variable "Delta" must have the delay value
                                           N number of TIMEQ can be used with different names for parallel operations with different flows.
                                  Power table updates can be used at the begining and at the end of the delay to update the power state of this block.
                                              eg:
                                                    if(Power_Flag){
                                                            power_updat = powerUpdate (Power_Manager_Name, Power_Block_Name, "Active")
                                                    }
                                                    TIMEQ(.............)
                                                    if(Power_Flag){
                                                            power_updat = powerUpdate (Power_Manager_Name, Power_Block_Name, "Standy")
                                                    }
                                   Power_Flag will be checked at the initialization stage to see whether the power is enabled or not.
                                   Power_Block_Name can be same or different based on the number of parallel operations.

                         Output handling
                                   Processed packets can be sent out to the corresponding ports as follows
                                              eg:
                                                    SEND(Output, port_token)          
                                            Output is the port name, it can be anything and it should be match with the available ports or the new ports that is goind to be added.
                                    if there needs to be a flow control then the packets can be enqueue in a output queue and wait for a signla.
                                    The signal can be either virtual event or global variable or handshake DS.

       ** For detailed syntax and features of script language please refer the Block documentation.

Analysis
              Latency and Power analysis

                      Image not found in local directory
                      Latency plot shows the total end to end latency, front end latency and backend latency in a single plot, when there is a change in pipline configuration with respect to speed or logic the latency will reflect it
                      Power plot shows the Average power and instantaneous power in a single plot. The instantaneous power is the consolidated power of all the device at each instance.
                      if there are any additional power state or additional device or additional operation in a specific block the power plot will reflect it.

              Buffer Occupancy
                     Front end buffer occupancy,
                      Image not found in local directory
                      MoP and Decode are independed flows and it can operate parallely, the MoP buffer occupancy shows activity 0.2us, upto that the MoP flow was idle.
               
                      Back end buffer occupancy,

                     Image not found in local directoy
                      ROB and Issue Queue occupancy shows the number of instructions that are waiting in each stage during the entire simulation.
                      This kind of analysis used for determining the buffer size as per the worst case and best case scinario.
                      Also this can help us to debug if there is any deadlock in the flow.

              Order of completion
                      In order commit and out of order completion.
                      Image not found in local directory
                      Out of order completion is the actual completion of execution  due to instruction level parallalism, but to maintain the standard operation the instructions must commit in order.
                      Commit stage will hold the instructions in ROB and expires it as the expected instructions get completed.


              Statistical Analysis
                      Architecture setup block provides the consolidated statistics during the simulation time. The number of statistcs sample can be configured in the architecture setup block and also linked to the specific blocks to sync with the Architecture setup(such as integrated cache).
                      Sample Statistics

Page_Table_Utilization_Pct_Max      = 0.8166666666667,
Page_Table_Utilization_Pct_Mean      = 0.8166666666667,
Page_Table_Utilization_Pct_Min      = 0.8166666666667,
Page_Table_Utilization_Pct_StDev      = 0.0,
Page_Table_Delay_Time_Max     = 5.8333333333333E-9,
Page_Table_Delay_Time_Mean    = 5.8333333333333E-9,
Page_Table_Delay_Time_Min     = 5.8333333333333E-9,
Page_Table_Delay_Time_StDev   = 0.0,
Page_Table_Memory_Used_By_L2_TLB_MB_Max      = 2.8E-5,
Page_Table_Memory_Used_By_L2_TLB_MB_Mean      = 2.8E-5,
Page_Table_Memory_Used_By_L2_TLB_MB_Min      = 2.8E-5,
Page_Table_Memory_Used_By_L2_TLB_MB_StDev      = 0.0,
Page_Table_Memory_Used_By_Total_MB_Max      = 2.8E-5,
Page_Table_Memory_Used_By_Total_MB_Mean      = 2.8E-5,
Page_Table_Memory_Used_By_Total_MB_Min      = 2.8E-5,
Page_Table_Memory_Used_By_Total_MB_StDev      = 0.0,
Page_Table_Throughput_MBs_Max      = 5.6,
Page_Table_Throughput_MBs_Mean      = 5.6,
Page_Table_Throughput_MBs_Min      = 5.6,
Page_Table_Throughput_MBs_StDev      = 0.0,

Bus_1_Utilization_Pct_Max     = 6.55,
Bus_1_Utilization_Pct_Mean    = 6.55,
Bus_1_Utilization_Pct_Min     = 6.55,
Bus_1_Utilization_Pct_StDev   = 0.0,
Bus_1_Delay_Max               = 2.498E-9,
Bus_1_Delay_Mean              = 1.6838549618321E-9,
Bus_1_Delay_Min               = 1.6659999999998E-9,
Bus_1_Delay_StDev             = 1.1688195402913E-10,
Bus_1_IOs_per_sec_Max         = 5.24E7,
Bus_1_IOs_per_sec_Mean        = 5.24E7,
Bus_1_IOs_per_sec_Min         = 5.24E7,
Bus_1_IOs_per_sec_StDev       = 0.0,
Bus_1_Input_Buffer_Occupancy_in_Words_Max      = 2.0,
Bus_1_Input_Buffer_Occupancy_in_Words_Mean      = 0.4146341463415,
Bus_1_Input_Buffer_Occupancy_in_Words_Min      = 0.0,
Bus_1_Input_Buffer_Occupancy_in_Words_StDev      = 0.5078942542185,
Bus_1_Preempt_Buffer_Occupancy_in_Words_Max      = 0.0,
Bus_1_Preempt_Buffer_Occupancy_in_Words_Mean      = 0.0,
Bus_1_Preempt_Buffer_Occupancy_in_Words_Min      = 0.0,
Bus_1_Preempt_Buffer_Occupancy_in_Words_StDev      = 0.0,
Bus_1_Throughput_MBs_Max      = 838.4,
Bus_1_Throughput_MBs_Mean     = 838.4,
Bus_1_Throughput_MBs_Min      = 838.4,
Bus_1_Throughput_MBs_StDev    = 0.0,

Cache_D1_Cache_A_Hit_Ratio   = 79.84,
Cache_D1_Cache_A_Miss_Ratio   = 20.16,
Cache_D1_Cache_A_Number_Entered      = 1261,
Cache_D1_Cache_A_Number_Returned      = 1249,
Cache_D1_Cache_A_Prefetch_Completed      = 26,
Cache_D1_Cache_A_Prefetch_Issued      = 26,
Cache_D1_Cache_Buffer_Occupancy      = 12,
Cache_D1_Cache_Buffer_Overflow      = 0,
Cache_D1_Cache_Latency_Avg    = 4.3211539631705E-8,
Cache_D1_Cache_Latency_Max    = 2.5491E-7,
Cache_D1_Cache_Latency_Min    = 4.9999999999991E-9,
Cache_D1_Cache_Read_Hit_Ratio      = 0.0,
Cache_D1_Cache_Read_MBs       = 4.56E-4,
Cache_D1_Cache_Read_MBs_per_Second      = 91.2001824003648,
Cache_D1_Cache_Total_Blocks_Evicted      = 0,
Cache_D1_Cache_Total_Blocks_Write_Backed      = 0,
Cache_D1_Cache_Total_MBs      = 0.006492,
Cache_D1_Cache_Total_MBs_per_Second      = 1298.4025968051938,
Cache_D1_Cache_Total_Reads    = 193,
Cache_D1_Cache_Total_Writes   = 1057,
Cache_D1_Cache_Utilization    = 79.608492550318,
Cache_D1_Cache_Write_Hit_Ratio      = 94.4181646168401,
Cache_D1_Cache_Write_MBs      = 0.006036,
Cache_D1_Cache_Write_MBs_per_Second      = 1207.202414404829

MC_DRAM_DRAM_Command_Queue_Count      = 64,
MC_DRAM_DRAM_Command_Queue_Max      = 1.0,
MC_DRAM_DRAM_Command_Queue_Mean      = 0.5,
MC_DRAM_DRAM_Command_Queue_Min      = 0.0,
MC_DRAM_DRAM_Command_Queue_StDev      = 0.5,
MC_DRAM_DRAM_Read_Bytes       = 1024,
MC_DRAM_DRAM_Read_IO_Count    = 64,
MC_DRAM_DRAM_Read_IOs_per_Second      = 6.4E7,
MC_DRAM_DRAM_Read_MBs         = 0.001024,
MC_DRAM_DRAM_Read_MBs_per_Second      = 1024.0,
MC_DRAM_DRAM_Read_Removal_Position      = {64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
MC_DRAM_DRAM_Total_Bytes      = 1024,
MC_DRAM_DRAM_Total_Delay_Max  = 5.0000000000002E-9,
MC_DRAM_DRAM_Total_Delay_Mean      = 2.91675E-9,
MC_DRAM_DRAM_Total_Delay_Min  = 1.6669999999999E-9,
MC_DRAM_DRAM_Total_Delay_StDev      = 1.3817511308119E-9,
MC_DRAM_DRAM_Total_Entered    = 64,
MC_DRAM_DRAM_Total_Exited     = 64,
MC_DRAM_DRAM_Total_IO_Count   = 64,
MC_DRAM_DRAM_Total_IOs_per_Second      = 6.4E7,
MC_DRAM_DRAM_Total_MBs        = 0.001024,
MC_DRAM_DRAM_Total_MBs_per_Second      = 1024.0,
MC_DRAM_DRAM_Total_Refresh_Pct      = 0.0,
MC_DRAM_DRAM_Total_Removal_Position      = {64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
MC_DRAM_DRAM_Write_Bytes      = 0,
MC_DRAM_DRAM_Write_IO_Count   = 0,
MC_DRAM_DRAM_Write_IOs_per_Second      = 0.0,
MC_DRAM_DRAM_Write_MBs        = 0.0,
MC_DRAM_DRAM_Write_MBs_per_Second      = 0.0,
MC_DRAM_DRAM_Write_Removal_Position      = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}