Verilog_Sim
Script_Language_Interface / Verilog
Block Name: Verilog_Sim
Code File Location: VisualSim/interfaces/verilog/Verilog_Sim
This block provides the user with the ability to add a timed interface between VisualSim and Verilog. The timed interface is the interface operation where both the VisualSim and Verilog simulator are synchornized so that the transfers across the interface are accurately performed according to the arrival time. The user sets the parameters according to the anticipated co-simulation interface timing, based on the Time_Resolution, Start_Time, and Stop_Time. The menu attribute for Time_Base will align the time entries to coinside with the Verilog time boundaries.
To use the Verilog interface, a GNU gcc compiler is required and the Verilog Simulator. If you using the 32-bit interface, then use the 32-bit gcc. Similarly, the 64-bit version must use a 64-bit gcc compiler. The Windows Installer, Linux Installer and MAC Installer are available at the respective links. The default support is for ModelSim. For all other Verilog Simulation, please contact Mirabilis Design Inc.
The Use Model for the Verilog_Sim is to model transactions between the two simulators with a simple timed interface to limit simulator interaction. Either simulator can be the initiating, or master, simulator in the co-simulation.
Note: If using Verilog on Windows, the gcc compiler from Mingw (g++ 3.0.x or higher) must be included in the PATH environment variable. For Verilog on UNIX, the gcc compiler (g++ 3.0.x or higher) must be in the PATH. The simulator name and path must be set in VisualSim startup script (VisualSim.bat for Windows and VisualSim.sh for UNIX). VisualSim uses sockets to connect with the Verilog simulator. A default socket is provided but the user can modify this in $VS/bin/vsconf.bat (.sh).
Refer Oscillator Demo Model.
Parameter |
Explanation |
Type |
Example |
Time_Base |
Time_Base attribute is based on SystemC nomenclature, used to align timeResolution, Start_Time, and Stop_Time to boundary values. |
- |
Verilog_NS |
timeResolution |
This is the smallest time value that the interface between Verilog and VisualSim will communicate across the interface. The value has a time base as expression in the Time_Base parameter. |
Double |
1.0 |
Start_Time |
This is the time to initiate the Verilog simulation to start after the VisualSim model has started. The value has a time base as expression in the Time_Base parameter. |
Double |
0.0 |
Stop_Time |
The Stop_Time is the time after the start of the simulation when the interface is disabled. The value has a time base as expression in the Time_Base parameter. |
Double |
100.0 |
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