Verilog_Cosim
Script_Language_Interface / Verilog
Block Name: Verilog_Cosim
Code File Location: VisualSim/interfaces/verilog/Verilog_Cosim
Note: The file name and file path for the Verilog file must not contain '_" and numbers.
The Verilog_Cosim block is instantiated in a model at the location where an existing Verilog file must be added to the simulation. If a Verilog_Sim is also instantiated in the model, then the interface of this model with Verilog transfers time across the interface. If the interface is purely functional and no timing needs to be transfered, then the simulation can be an event-triggered. The Verilog_Sim will not be instantiated in this case.
The Use Model for the Verilog_Cosim Block is to add Verilog_Cosim blocks within a model where ever a connection to Verilog is desired. One 'Verilog_Sim' block per Verilog model is needed in the case of the 'Timed Interface'.
To use the Verilog interface, a GNU gcc compiler is required and the Verilog Simulator. If you using the 32-bit interface, then use the 32-bit gcc. Similarly, the 64-bit version must use a 64-bit gcc compiler. The Windows Installer, Linux Installer and MAC Installer are available at the respective links. The default support is for ModelSim. For all other Verilog Simulation, please contact Mirabilis Design Inc.
Step 1: Drag the Verilog_Cosim block from the library onto the Block Diagram Editor.
Step 2: Configure the block with the values for the two field.
Step 3: Configure the port names by right-click on the block and selecting Configure Ports. "Add" a port, enter whether input or output and specify the Verilog Type in the Remote_Type column. All Verilog data types are supported. For a list of the supported data types, please refer to Chapter 8-Interfaces.
Step 4: From Menu-Bar, select "Generate Wrapper".
Step 5: From Menu-Bar, select "Compile Wrapper".
When the Generate Wrapper and Compile Wrapper is selected, this operates on all SystemC, C Interface, Verilog and VHDL blocks in the model.
See Also:
SC_Module, SC_Sim.
Refer Oscillator Demo Model.
Parameter |
Explanation |
Type |
Example |
Verilog_Module_Name |
This field is used to enter the name of the Verilog file. |
String |
"Module1" |
Verilog_Module_Path |
This is the path to the .v that contains the Verilog module code. The path can be an absolute path to the Verilog file. If this is within the VisualSim, then it will listed as Verilog/bitmodel / bitmodel.h. |
String |
"Verilog/bitmodel / bitmodel.h" |
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