Release Notes 2320

Release Notes for 2420
Library

Thermal block to capture heat and temperature per device
UCIe die-to-die IP model
Crossbar
Arteris NoC
Tileink cache coherency
Cache coherency IP
LPDDR5-X
Updated Battery blocks
Reduced the number of fields required by all IP blocks to 7. replaced Processor_DS with Hardware_DS
Generate UPF, VCD and SystemVerilog files for testing power system
Updated parser for GEM5 and ARXML to VisualSim csv format

Features

Reorganized block and application templates
Updated training class material for ease-of-understanding, new libraries and basic modeling concepts
Link Post Processor with Regression and multi-core simulation
Updated all documentation to a new and uniform format

Release Notes for 2320
1.    10BaseT1S
2.    TC10
3.    CAN XL
4.    Avionics
5.    Class file Encryption
6.    TTEthernet Integration techniques – Timely, Shuffle, Preemption
7.    Failure Analysis

a. Single Point Faults

i. Logic Circuit Failure

ii. DMA Illegal Sequence

iii. Timing Inconsistency: Clock Sync Drift + Contention

b. Multi-Point + Latent Fault(s)

i. Voltage Drop

ii. Transmission + CRC Error

c. HW Failure: Core + Memory + Noise

d. SW Failure: RTOS + RD/WR Memory + Deadlocks + Livelocks

e. Network Failure: Loss Communications + Message Corruption + Excessive Delays

f. Network Failure: Unexpected Message Bursts + Wrong Message ID

g. Network Failure: Node + Message Spoofing + Bad Addresses + Overloading

h. Brute Force, DDoS Attacks: Denial of Service, etc.

8.    PCIe 6.0
9.    UCIe
10.    Antenna modelling
11.    Deep Neural Networks
12.    Heat and Temperature
13.    Address based crossbar
14.    ARM Cortex M55
15.    Tarmac support for RISC-V processors
16.    ADAS demo
17.    Tutorials on TSN_Switch, CMN600

B. Demo
1.    TC10 Sleep_Wakeup : VS_AR\demo\networking\TC10\ TSN_Switch_TC10_Demo_Model.xml and Multi_TSN_Switch_TC10_Demo.xml
2.    10Base-T1S : VS_AR\demo\networking\10_Base_T1S\ ECU_Sensor_10Base_T1S.xml
3.    CAN XL : VS_AR\demo\automotive\CAN_Bus\ CAN_XL_Demo.xml
4.    State machine demo : VS_AR\demo\performance\IoT\ IoT_Model_5_Nodes_V6.xml
5.    Fault injection on Clock Synchronization: VS_AR\demo\networking\TTEthernet\ Clock_Sync_Fault_Injection_Demo.xml

Release Notest for 2210
1.    Cycle accurate processor blocks for behavior modelling
2.    NoC (Non Coherent)

a. Arteris NoC
b. Generic NoC

3. Cache Updates

a.    Prefetching
b.    Flow control
c.    Debug port
d.    Data flow stats

i.    hit or miss in each cache that passes through
ii.    time it took in each cache (Buffering and processing)
iii.    latency as number of cycles

4. AXI

a. Pipelined flow enabled
b. Multi Master Multi slave plotting

January 2021
------------------
1) run the openwebstart successfully and updated HTML code and JNLP file for distribution.jnlp, updated jars with java 14
2) updated licenseutil.java bug with opening library blocks for openwebstart
3) systemC batch file updated in VS_AR/bin
4) fixed the demo models
5) updated multicore java file as requested by esol
6) created traces for cpu instructions, cache and memory from gem5
7) updated postprocessor to support older version as well
8) updated batch file threadsimcore.bat and .sh

February 2021
---------------------
1) updates in the VisualSimBatchModeSimulator java files, by adding parameter name and values.
2) updated the cloud version and corresponding 8 java files
utility funtion
actorgraphgframe
basicgraphframe
actorcontrooller
saveingplotter
savingdisplay
top java
Line writer
3) included jar files to the jnlp file
4) updated the web.properties file along with the documentation
5) worked around documentation, pynq and s2c technical specs

March 2021
--------------
1) Dram block bug fixed - duplicate read packet for same id.
2) Added refresh parameter - default is true.
3) virtual machine bug fixed - related to delays and TIMEQ and updated virtual machine compiler , virtual function, queue item and scheduler queue.
4) worked with Akash on assembly instructions for different arch
5) update the python code according to the requirement from Akash's model
6) Assist Riya with the systemC documentation and provide it to customer
7) Generated intermediate files at the compile time from gcc - .s,.o,.i
8) create the list of model for the opencloud template and fixed few of the models.
9) Updated NPE in line writer
10) csv writer updated

April 2021
---------------
1) created multi core model for pynq
2) Created a instruction behavior code for around 30 arm instructions for the processor models.
3) Server block updated for utilization stats
4) updated the error message for the expression list for undefined ID.
5) Xilinx PYNQ performance Evaluation Kit which includes all the demo models from visualsim and traces from gem5.
6) Worked on the latest gem5 for Jpl guys.
7) made latest gem5 compatible with VisualSim architect.
8) created disassembly files for Akash from gcc compiler and godbolts
9) created the document on the VisualSim logos and GUI for the s2c
10) Assist jpl folks on the gem5 installation bugs.
11) Provided details about the front page - window size, logos and vs docs to s2c
13)

May 2021
---------------
1) updated custom_source.
2) Queue and Server bug fixed - about null pointer exception at the wrapper method
3) system resource extend update with the statistics fixed along with Diagnostic block
4) Scheduler_SW bug fixed with scheduler_type = FCFS+preempt
5) customer_traffic updates with the parameter settings
6) cjpeg files for comparison and generated the dissembly file for the same for 32 nd 64 bit
7) Reviewed the Cpp code provided by s2c for windows license
8) Worked on generating the python code executables and run it against gem5. it fails for x86 architecture

June 2021
----------------
1) Digital debugger and architecture setup updated
2) scheduler_sw duplicate packet bug, added warning message in the console log and in the listen to block. if the duplicate packet found.
3) created explanatory video for visualsim cloud
4) Diagnostic blocks updates :
1.    Added an 'activate' parameter to the block for activating/deactivating the block
2.
1.    Added a Type (Avg/Min/Max) parameter to the Latency/BufferOccupancy/Utilization (LBU) Stats.

1.
1.    Script Variable Monitoring Support added for Integer, Double & Array (for Integer and Double data types)
2.    Add an optional ‘Type’ Parameter to check the Avg/Max/Min value that the Variable contains for the entire simulation.
3.    Added the support for an optional ‘Correlate’ column to track the values of a correlated array(To be entered by the user in the input file under ‘Correlate’ column) – Latency per ID use case. Added the support for an optional ‘Tracker’ column to track the values of one array with respect to another array. Output in the Tracker Column –<Value_in_Correlate_Array>_<Corresponding_Value_in_Stats_Array>
5) update in Virtual machine - profiler bug
6) Python parser to create the plt file for AXI dataset files
7) Out block updates - with the support for model parameter, variable list and string values
8) Power block update - related to listen to block
9) bug with Max_buffer Occupancy (a+1) case in system resource and system resource extend
10 ) Linear port update
11) composite token update
12) recent updates in the saving plotter, line writer and saving display for command-line execution
13) New VisualSim front page,GUI and logos etc
14) License Files error message updates for VisualSim.
15) created 40 benchmark executables provided by jpl, parserd the traces and generated the output file in visualsim format.
16) run the output traces on visualsim models for testing the real hardware
17) License Manager updates for the s2c includes - pop up window incase of error, title bar update on the pop-up and error message updates.
18) created an interface between cpp and java for window license check feature for s2c
19) created batch files for windows and Linux to start the server and open the tool
20) created and interface between c and java for Linux license check feature for s2c
21) OEMS around 50+ documents on the visualsim for s2c
22) front pages updates according to the customer requirement for s2c
23) post processor error message and title windows updated for s2c
24) visualsim title window updated to Genesis and   images updates for s2c.
25) Java heap space bug fixed in virtual machine
26) updated diagnostic documentations

Release Notes for 2110
Library updates:
1.    DMA :
a.    Outstanding req parameter accepts empty {} which internally is interpreted as all channel having outstanding count = 1
b.    Additional stats were generated from the DMA per channel (Utilization ) -> can be obtained from Architecture setup block
c.    If number of requests overflow the buffer size, then error was thrown. This was removed and now the overflown frames are simply rejected out via reject port
d.    A_Task_Flag was set to be true as write frames were not coming back to the DMA
e.    Error messages were updated
2.    RISC-V demo model – model bugs
3.    TileLink class files were updated – bug fixes
a.    TileLink fragments frames and occasionally goes -ve frame size
b.    Variable overwrite issues were fixed
4.    Python block bugs were fixed
5.    CMN600 – Memory interleave demo model was added to the tool
6.    CAN Bus document was updated
7.    AXI Bus document was updated
8.    Smart Resource duplicate packet issue was fixed
9.    Intel FPGA models updated
10.    CAN Bus fixes and updates to work with ETH library
11.    Infotainment demo models (part1,2,3,4)
12.    NoC demo models were updated – for University (Ottawa)
13.    GEM5 wrapper code was updated and new demo models were created – AXI+HW_DRAM, Infotainment model etc..
14.    Cortex R5 demo model was updated – bug fixes
15.    PCIe – bug fix: -> At the script where the decrement function was defined, a flag was being used and that flag was never reset after use. Fixed it.
16.    SRIO, PCI-Rad bug fixes
17.    Power and Performance verification for Processors were done
18.    Processor:
a.    Waiting from the return of requests from Cache was added
b.    Updated the usage of Hit_Ratio parameter
c.    Bug fixes on the Number of Instruction Per Cycle parameter value -> If the number of instructions available in the instruction array was less than the parameter value, then an array out of bound exception was thrown. Fixed it.
19.    Clock Sync is now perfectly synced. If the TIMEQ is used for Clock Sync and Clock period is 5.0 nsec, then there wont be any Sync Delay for frames coming in at 5.0 nsec, 10 nsec, 15.0nsec etc.. Earlier, the frames would have to wait for next clock edge when the frame comes in at 5.0nsec or 10.0nsec etc.
20.    Generic Switch Block was created – (Used by Rajesh)
21.    Mapper Task Number bug was fixed
22. Custom Traffic Block    T_Interval , T_Pause and Number of Transactions works with random numbers
23. File Reader    Unable to read the d.txt and required confirming YES/NO for overwriting
24. Was not able to read files in the traffic Generator and was giving error in the output values

September:
1) System Resource and System_Resource_Extend time array and trace array bug fixed
2) fixed the fragmentor code of the AHB block
3) fixed the issue on max occupancy -Scheduler_HW
4) build gem5 for ARM ISA and added features like command line debugger, graphical       debugger, made visualsim and gem5 work together, founds command to run the program in multicore and single-core.
5) added feature to run in se mode.
6) updated code in dram_cntrl.cc. -gem5 related
7) tested the AHB - LC code

October
-----------------
1) added support for full system in gem5 - booting Linux on top of gem5.
2) generated stats for gem5 - arm executables stats
3) generated stats for qemu - logfiles etc
4) Build the gem5-RISCV.
5) added feature to run the gem5-RISCV and visualsim,
6) added feature to run in se mode , single core and multicore
7) generated riscv-executables- cross compiler
8) documented everything in reference guide - qemu , gem5-arm and gem5-riscv
9) fixed the issue with gem5 build,resolved runtime errors , able to run the visualsim for iteration zero but an error occurred- resolved the issue
10) solved the errors while importing some files for riscv
11) updated a lot of c++ files in gem5-riscv and updated the executables
12)fixed the issue with jar file on Linux, updated the shell file
13)fixed the Ashish's issue - error in shell file and in the linux path output file code - batch mode pp error
14)updated the python code in order to run the file and generated object , header , executable in riscv compiler
15) generated tempfile, write and read object file sucessfully - file responsible to work with Visualsim for gem5-riscv
16) updated postprocessor multicore, changed the configure activity gui and plotmanager in order to run in multicore-disables the option for writing to index file

November
---------------------
1) updated the reference guide and documentation for gem5
2) fixed dma issue -tested and complete - dma width parameter bug fixed
3)work on the documentation and packaging of gem5 - arm and riscv
4) error message update for if-else, added highlight for the block if errors occur in virtual machine
5)modifed the errors in composite token and database block ,added highlight for the database block, made the error more user friendly
6) created the stats for gem5 - memory, cache and CPU core
7) updated the database block - the bug with id and time
8) updated code for forloop in virtual machine, ud, vf, vc java files and nested for loop issue - fixed
9) fixed the bug in custom_block code
10) added classpath and javapath for postprocessor batch mode, updated the code ppcpadded buttons in the gui of ppcp.java for input path and csv file , then removed the code from ppf.java for generate batch.shell menu bar. Addde new code in the indexbatch.java to generate the batch and index file at the same time from one place
11) updated QoS block was throwing null pointer with reject port and The QuantityShared block has a bug. The dimension, priority and quantity ports require int. make them General and then internally test to see f the value is Int.
12) dynamic mapper - bug in brake model when accepting input.feildName. Was fixed in the last patch, but the java file is not updated on the github
13) bus arbiter width bytes parameter couldn’t be linked -fixed
14) database error message update and npe fixed
15) CSVwriter fileOrURL paramter enhancement

December
------------------
1) fixed csv writer - added parameter and postprocessor update -DStoCSV conversion, savingfile,readmodelxml from /plot for csv writer - linked to postprocessor
2) updated vstooltip , class utilities to java 14
3) fixed launch demo from website
4) added feature for script block fonts and style
5) added rsyntax jar in the jnlp file
6) updated models while doing testing
7)fixed bug in the AMBA_AXI, the bug was in utilityfunction.java
8)fixed the bug in AMBA_AHB - write operation was not working , so updated the linear controller code
9) timeq-sync issue - updated virtual machine

January
---------------------
1) run the openwebstart and updated HTML code and jnlp file for distribution.jnlp
updated jars with java 14
2) updated licenseutil.java bug for openwebstart
3) systmC batch file updated in VS_AR/bin
4) fixed the demo models
5) updated multicore java file - requested by esol
6) created traces for instruction , cache and memory
7) updated postprocessor to support older version also
8) updated batch file threadsimcore.bat and .sh

New Feature:
1. Generic NOC (ring and mesh topology)
Traffic profile stats
Throughput across wire
Wire delay
2. Cache coherence
Snooping
Directory based
3. ACE Bus

4. TLB
Simplified the code and logic
converted into a class file

Bugs fixed:
1. Cache
Removed “Block Configuration” parameter and simplified the code
Bug in associativity replacement policy
Bug in prefetching with multilevel cache
Bug in Hit miss ratio function
Added VIPT mode

2. AXI
Duplicate packet generation
Added arbitration delay in packet transaction
Pipelined read request at slave
Power for TIMEQ delays

Release Notes for 2030
New Library

Ethernet Switch, TileLink, CRC, Checksum, RTOS, Heat and thermal output from Battery block, network failure library, CMN600, ARM A77, ARM A63, ARM A65, ARM Z1
Comparator

to compare the results from two separate runs and check their fail/pass status based on listed criteria

XML comparator

looks at two versions of the same model and lists the differences. XML Comparator also does static port connection check and lists all the ports associated with a relation.

GNUPlot interface

to generate plot datasets in GNUPlot format.

It is very useful for timing diagrams and state-based activity diagram.

ARXML support

for Automotive traffic standard - ARXML

to generate CAN and Ethernet network traffic

First generation failure analysis modeling concepts
Batch Generator

Generates a .bat or .sh file which lists all possible parameter combination for any particular model selected, with the parameters selected as per users choice.

Multi Thread batch mode execution

Distributes each simulation setup in the Batch Generator file to a core.Maximizes the use of the single machine processing capacity. Does require 8 GB of minimum memory.

Diagram generator

Support for diagram generator using an Open Source tool.
Activity, State, Timing, Component and Object diagram.

Hardware in the loop

Developed custom interface to S2C FPGA boards
Support for both Master and Slave IP on the FPGA is supported

New Models

Video Display System, Data Center, Software Defined Radio, 5G Wireless, braking system, Ethernet Switch+CAN+Gateway, TSN+CAN+Gateway, Intel FPGA, Xilinx Ultrascale and Xilinx Zynq, Microsemi

New Video

Training Series, short videos on data structures, traffic, queues, System Resources, Servers, Traffic and Debugging

Migrated to java 14

Java 8 has been end-of-life and there were errors that were not being fixed

Feature enhancements

Full-featured Text Editor with support for syntax highlighting, line numbers, search and font management.
Integrated Diagnostic block with System resources, queues, servers and channels to test error conditions
Support for spaces and empty arrays in Database and Memory_Init
Added 45 error statements
Hierarchy blocks can be saved in UserLibrary
Get a document that display all the parameters, blocks, hierarchies, ports, wires and variables
Simulation speed:

Increased speed by 40%.

New methodology developed to increase simulation speed in high processing Script by up to 8X.

Support for view plots from generated Web HTML documentation
Print out of all virtual connections and resources when the wrong connection is made
Added new RegEx to help the user consolidate all custom statistics and print out in one location.
DMA:

Support multiple outstanding request.
Without waiting for an acknowledgement, DMA will carry out tasks till the outstanding request count is reached.

Script

Detection of errors.
Add requirement of BREAK for CASE-Switch
Error messages for arrays
Initialize variable before for loop
GTO can have a string
Support for Find in Script file

Release Notes for 2010
New Features
1.    Automatic layout – lets the user allign the wires automatically and in a presentable manner
2.    Unit Constraint solver – This is a new static check feature that was added to check whether the units are properly matched, to check whether the model design is consistent or not
3.    Diagnostic block – This new module will check and analyse the architecture dynamicaly and capture all the mishaps happening. Like whether packets are getting dropped, warnings on improper configuration etc.This new module will also let the user specify some constarints that the user wishes to check. If the condition are not met, the full statistical analysis of that module will be printed at the point in time itself.
4.    GEM5 Wrapper – This is a new addition to out alreasy existing large library. This module acts as the interface beween GEM5 simuator and VisualSim Architect. Linux environment is required.
5.    Traces – Traces are generated for all resources and architectural blocks
6.    DMA – DMA had been updated to have the following featues:

a.    Alternate between Idx 1 and 2 sequence was updated
b.    Input Data Structure field
c.    Traces
d.    Statistics
e.    Replaced pull-down with line

7.    AHB – Fragmenter has been added
8.    Udated RegEx – getResourceActivity will give the current length of all the queues in the resources listed in the database resource column
9.    Warning message for unused variables and Queue usage
10. 16X16 size AXI Bus
11. Updated Integrated cache
12. Added support for AHB, PCIe and DMA for the ardware_DS data structure
13. Fixes for processor to support external cache, external SystemResource
14. Speedup the Listen to Block and Listen to Port when there is a large data being sent to the Display

Release Notes for 1940
New Features

Interface to software execution on Processor ISS

Distirbute simulationa cross multiple cores

Tight integration to Excel and GNUPlot
Complete revamp of Cache and Memory

Eleven new library components

New Library

CRC and Checksum network components
Integrated_Cache block that combines stochastic and address-based with new features
AMBA AXI bus has a new version with 16X16 ports
TSN library with Scheduler
TCP library
Over 10 different schedulers for use in hardware, RTOS and network applications
Integration to Excel
Wrapper to operate with GEM5
New Processor block to support External cache, Out-of-order execution,

Library Updates

Post Processor supports Array Plotter and Bar graph
Update to AFDX, TTE and DRAM blocks
New SystemC interface to support System 2.3.3
DRAM and DMA support variable width
CAN Bus- added power management and simultaneous 11 and 29 bit processing
AXI- support 16X16 ports
Application templates- TCP, TSN, CAN usage, CRC, Checksum, Memory, Integrated_Cache, Software_Defined_Radio, Application of schedulers, Writing output for GNU Plot, TCP/IP and Excel
Reordered parameters in multiple blocks
Added Save and View for ArrayPlotter and Bargraph
Failure analysis
Fault Injection, Detection and Resolution examples

Bug fixes, Documentation and Errors

Set fonts and sizes in VisualSimConfig.Properties. Now applies to all parts of VisualSim
Language naming moved to .VisualSim folder to permit read-only install location
Fixed error messages in many blocks to suggest solution
Reduced the number of new fields created across buses and memories
Fixed the use of random in cache and Instruction generator block
Prevent deadlocks between Events
GNUPlot did not display when a dataset did not have a value. Now added default values
Made fileOrURL and Data_Structure_Name to be symmetrical in Traffic block
Renamed plot legends for buses and memory
Removed start delay in AXI and Memory. This forced the Hello messages to be delayed.
More descriptive way file names for the power statistics file
Ensured that row precharge worked correctly for the second request to a different row
DeviceInterface does not update if the field exists
Fixed fileParameter to support hierarchical parameters
0L is no longer converted to string in InitVariable
Instruction generator had the wrong length for every start of the simulation
Delay block generated an error when double/double was used in the Expression.
Path in Script block now supports "" for the file name
Support instructions from Database for DynamicMapper
State change in Power Table supports all blocks including custom block
Not enough description on LocalPreferences module
- Motor energy harvester cannot find class file (Linux)
- "VisualSim_1940_64.jar' is not marked as executable
- "
- "com.microstar.xml.XmlException: XML element ""entity"" triggers exception. in [external stream] at line 2 and column 81
- "
- Duplicate memory creation : Color_Array
- "<entity name = ""PullConsumer"" class= ""Visualsim.actor.corba.PullConsumer"">""
- java.lang.NoClassDefFoundError: org/omg/CORBA/UserException"
- DRAM cannot locate Memory_Controller: none_Mem_Ctrl, suggest edit.
- "Error with getCell RegEx
- VisualSim.kernel.util.IllegalActionException:
- Block : Dynamic_Mapper.DynamicMapper
- Error : Task_Number Expr (getCell (Database_Lookup, Task_Name, ""ID"")) not an integer:"
- Invalid Delay_Value Field Name ( Fld_Name_or_Dbl_or_Expr ) Parameter should be Double or String of Field Name in Mapper.
- Model Results/Block functionality not correct
- "cl' is not recognized as an internal or external command,
- operable program or batch file."
- Explanation : getDS = getRows("RT", NodeName,"Source_Node"), Check argument types, argument values, field names, and variables.
- Expression does not compile: SEND (status, Flow_Control_Name + " Block: " + Block_Name + " WAIT(" + Event_Name + ") complete.")
- LPDDR6_Mem_Ctrl (SDRAM) Block Parameter not found, suggest edit.
- "<entity name = ""Router_NEW"" class = ""VisualSim.actor.arch.ARM.Router_NEW"">
- Cannot find class: ViusualSim.actor.arch.ARM.Router_NEW"
- Bytes = port_token.A_Bytes_Sent + Data_Header, Check argument types, argument values, field names, and variables.
- Instruction Mnemonic (Instruction) not found for Execution Unit (SH4_List)Exception: Check Instruction_Set for match.
- "Parameter (Number_of_Banks) on LHS of expression (Number_of_Banks = 2^Number_Bits)
- Suggest modifying expression.
- "
- "Code Error
- "
- Database Reading issue
- Array couldnt be converted to a token
- "Error : Block Overlaps with (.FC_System_w_Multi_Switch.FC_Config.Database4) with Name: End_Point_DB
- Exception: : .FC_System_w_Multi_Switch.FC_Config.Database2 Name must be unique."
- NegativeArraySize Exception
- Unknown Error
- No values on Time data plotter
- "Active_File = readFile (Instr_File), Check argument types, argument values, field names, and variables.
- File not found none found for openForReading."
- no values on Text display
- no values on Text display
- "Error : Cache Reference (L2) expect to start with L_."
- L2 requires _ in between
- Null Pointer Exception
- Routing Table Reference
- no values on Time Data Plotter and cycle accurate memory
- Error : Destination_Name (1Clock) not found.
- no values on Text display
- Processor error
- "<entity name = ""JAlImageReader"" class= ""Visualsim.actor.lib.jai.JAlImageReader"">""
- java.lang.NoClassDefFoundError: com/sun/media/jai/codex/SeakableStream"
- "<param name = ""fileOrURL""
- value = ""file:/C:/VisualSim/VS64/demo/image_processing/demo_jai/goldhill.gif/>"""
- "Field_Description_B problem.
- Field Type is not recognized.
- Actual Type: String
- "
- unexpected characters after document end (found "<") in file:/home/mirabilis/Documents/VisualSim/VS_AR/demo/image_processing/DVB/Golden_Model_Database.xml at line 1930 and column 5
- "in .DSP_Top_Level_baseline.manager
- Because:
- URI is not absolute"
- No results on processor output
- Last Fragment not coming out from Bus Arbiter
- Issue with Regex execution
- Issue with Regex execution
- "Error : Cannot send to External Cache (Unknown)"
- not sure with tthe output result
- No Latency is plotted
- Same error with AVB_Setup, TTE_SetUp blocks. Need to change the blocks in the library. This block does not show error for AVB models. Error is with TTE. Need to change the TTE setup block
- The file is not available. The link fails
- Hyperlink fails
- The trigger port is not available.
- Data type Error
- Data Type not recognised in Insert block. Lower Case s should be used
- Switch Block has Parameter on the LHS of expression
- Branch instr taking too long to process error generated by processor
- Null pointer exception
- issue with regex execution
- "Address_Bit_Map (3), Check argument types, argument values, field names, and variables.
- "
- issue with regex
- Virtual Connection to Clock Align Block is not made
- memory controller issue
- null pointer exception
- "cannot use multiple '-' in script within a string
- ex: text = ""-------"""
- "powerUpdate issue
- "
- NullpointerException
- Buffer size is full in SR_Extend
- takes more time than usual to run
- getRows() RegEx is having issue
- No function found matching listenerFormatOutput
- No function found matching readerToString(string)
- Software mapper feild issue
- issues with Processor
- null pointer exception
- Latency is not plotted
- new error
- "
- Software Mapper is not accepting the ""Task_Destination"" format. Works for input.Task_Destination"
- Stack Overflow Error
- NPE
- "Txt file not present
- "
- The Clones are having issue
- NPE
- NPE
- instr is taking too long (BRANCH instr)
- No Such Element Exception

Script

Nested switch statement to prevent infinite loop
Create empty array
Assign computed values such as Queue length to a index of an array

Release Notes for 1920
New Features

Export to Web

VisualSim online

Clear Listen windows at the beginning of the next run

Output state plot from Power Manager and viewable in GNUPlot

New Java certificate for use within Browser

Automatic tool tip generation

New plotting for AXI, Bus, AHB, PCI and PCIe
Support DDR4

New Library

Check input fields and values at entry into over 100 blocks. Reduces cryptic error occurance.
ARM: A53, A72, A76
AMBA: CHI5, CMN600
RISC-V, Leon
NoC, SSD
BAE PCI
SystemResource_Extend support Non-Blocking FCFS
New blocks- Tracer and GNUPlot
getBlockStatus for QS_Resource block
Completely new set of statistics and error messages for AXI and Memory

Library Updates

CAN Bus- added support for new look-and-feel, signal and message routing, simultaneous 11 and 29 bit and error checking
Application templates- signal processor, software defiend radio, thermal, Cubesat, SSD, industrial systems with PowerPC, Xeon and RapidIO/PCIe, Avionics, Telephony, VoIP, SysML conversion example, Failure analysis
Zynq Ultrascale
GPU
Nvidia DrivePX
ADAS
Big-Little mobile system
TLB
Integration imaging algorithm with performance model
Open Flow Switch
Experimental system using a Discrete Optimizer
Demonstration for generation of html documentation
Jet engine
Programmable array controller- Industrial
Satellite modem
Media Server and Network Attached Storage
Traffic block supports URI format file naming
Support for recursive expression in PowerTable
Support for variables in PowerTable
Added full RegEx, Variables and fields in Mappers, SystemResource, Queue, Servers and Channel blocks
Modified parameter names for SystemResource, Mappers and Power Table
Append to array checks for type
Upgraded QS_Resource to be on-par with Queues and Servers
QS_Resource and Mapper/SystemResource can be in the same behavior flow
Double-click opens the Script code
Eiminate caches from calling itself
Routing Table and Database blocks support a separate file parameter field

Documentation and Errors

Removed the get from inside channel and send to inside channel debug messages that duplicates the Listen to Port information
New Reference card that covers all the library, GUI features and statistics
Added documentation for all the blocks did not have them prior
New Error message format added to all the blocks- block name, error description, suggested solutions and ID
Added online documentation for over 200 application templates
Error message for file path is specific
Dynamic instantiation now states that Simulation is required
Error reported when fields are left blank
Type controlled for input and parameter values. Reduce computational errors. Errors captured at both construction and run-time
OUT, IN, Mapper and Script blocks provide a list of possible destinations
Eiminated a number of Null Pointer Exception Error. For all other Null Pointer error, add some additional information to help the user identify the error.

Script

Support empty lines in loops
if-statement can have { brackets on the same or next line
Support for loops
Support nested While Loops
Switch-Case also support C format
Support upper and lower case method and keywords
New format for the List to Block that shows a better compiled view of the code
New error formats pin-points exact line in the code

Infrastructure

Support for Visual Studio 17 and gcc 4.8 for the C/C++ interface

All statistics are written to file at the end of the simulation in the same directory as the model

Errors are written to VisualSimConsolelog file

Added trace for all Bus blocks

Infinity caught as a error

All print-outs will use the same font- Courier

TrafficReader supports end-of-file and array generation

Better explanation when source is not available

Moved SystemResouce and QS_Resource names to a common field

Release Notes for 1720

Fixed Range Parameter
Pull-down Parameter with a fixed list of items
Expanded editor for text fields in block parameters
Expanded editor to directly access a file from within the User Interface
File chooser for Database block
Access Help documentation from the Parameter Window
Enhanced text editor
Migration from java to Java Webstart for faster download and access
Add user certification to prevent Web blocks
Power generator for piezo-electric, wind, solar, motor etc.
Battery model with support for different types of battery, life expectancy, capacity and discharge, multiple charging schemes, external thermal and shock impact. Statistics generated for charge input to actual use; surge current, peak consumption, average consumption, battery discharge, battery life, and battery capacity loss.
Power Manager and Power Table-

Naming: Support for different state names, transition cycles for each state, define variables for dynamic power value change
File Chooser for Power table entries
Asynchronous time-based state change using a table
Expressions for each state
Hierarchical power manager
Hierarchical statistics including average, cumulative and instant
Power consumed by state
Dynamic change of frequency for device and power
Dynamic change of state expression based on task
Generate GNU Plot for State change

New state change RegEx function

Node block have been upgraded for performance and new routing functions
Layer table supports full features error correction and retry
Support for hops and bandwidth to compute the routing table
All models updated for the new library blocks
Added a new VisualSim reference card for quick learning
New demonstration and application notes added

Release Notes for 1620

Auto Save
Restart and Checkpoint
Internationalization
New documentation and structure
New library organization for easy access
Updated Power Manager to support expression in the columns, improved performance
New RegEx functions for Arrays
New libraries- Fibre Channel, RapidIO, Firewire, Time Triggered Ethernet
Added support for power in Memory Controller and Cycle-Accurate DRAM
New front page for each access to content
Online application template to search and find new models
New tutorials for interfaces and buses
Rename Memory to Variables.
Added new support RegEx for the Variable- readAllVariable, readVariable and writeVariable

Release Notes for 1520

New Features

Pause and Restart enables user to pause a simulation at any time and save the simulation data. The saved model can be restarted from that point.

Cancel an Event

Now available from Java and Virtual Machine

Trace controller

View the debug messages from multiple blocks in a single view and save to file

View memory updates from all blocks in a single location

Arrays

New function to create a array.

Able to create arrays with 5 million items to define SSD of over 8GB

Reduced the steps to remove an item from the array

Added ArrayTokenInterface to the Array token that provides a improvement

Append to Array uses system.ArrayCopy that is now much faster

Simulation Performance

Fixed the priority inversion in the Circular Queue

Always pick the first empty one

Reduce the number of circular queues and the length of each

Speed up of event updates in Circular Queue

Reduced the number of methods and associated variables

Changed data structure save to integer tokens to reduce memory size and speed up processing

Virtual Machine

Speed up the block variables by changing the hashmap storage method

Supports Java 7. Moving to Java 8
Reduce internal data sizes to speed up initialization

Infrastructure Features

Restart

Pause model and save states/events/queues/memory content to file
Restart later from this point onwards
Future feature is to change memory values and virtual machine code. Can do it manually now.

Reduces simulation time for both debugging and repeated runs

Interface to FPGA Board

Connect the model to a FPGA board
Check implementation in the system context
Speed up complex processing using FPGA code
Can be used to connect to any device

Upgrade C++ code interface

Can connect to any compiled, executable or other code
Can be triggered by input or independently

New Libraries

Upgrade to RapidIO 3.1
Time Triggered Ethernet
Ethernet- Audio Video Bridging
Processor- Pre-emption
CAN Fast Data Rate
Upgrade for PCIe
AFDX
Zynq-7000
OpenFlow Switch

Release Notes for 1420

New Features

Block breakpoints can be unchecked when the model is paused by arriving at a Breakpoint. This means that the model can proceed from that point onwards without stopping for this breakpoint.

Classes (XML and Java) can now be located anywhere, as far as the root directory is in the CLASSPATH. Also special characters can be included in the directory name and the directory can on a different Drive.

Full support for Verilog

Full support for Dynamic Instantiation including dynamic instance creation, support for all blocks and memories, show instances on the Editor and Listen to Block at all instances

Highlights exact block that has the error in a multi-level model.

Time to open a new model has been reduced considerably, especially for large models

GUI overlap problem has been fixed

“stop animation” is no longer required before performing a second “Animate Execution”

Interaction between Digital debugger and Animation has been resolved. Model can be animated in debug mode

Undo option to restore on accidental deletion of dependent Parameters and BDE components is improved

As a new feature the parameter name and memory names must not overlap

Specific sequence of connections for Multiports is not required any more

Block with error during simulation will be highlighted in Instances, classes and Hierarchical blocks with more than 3 levels.

Release all memory at the end of a simulation. Reduces memory usage significantly in all models.

RegEx and Java function to create and cancel a event using a ID.

New version of Explorer with a Pup-Up VisualSim Architect on the Web

Export to HTML has now a configuration for view-only, simulation and popup

Upgrade jar files for Java 1.7_u51

New library: AFDX

New Library: Audio Video Bridging

New Library- Xilinx Zynq 7000

New Library: Autosar

RegEx: 18 new RegEx functions

Support for Java 1.7 and Java 1.7 64-bit

Added Preemption to Processor with an example for external processing

Added Duplex to the Routing Table Database

Use the Routing_Table without the Node blocks

New RegEx function for Add and remove a link

Added a Block Reference parameter to the Virtual Machine. This will enable blocks used in Hierarchical and Class instance to be used without having to enter a unique value for the parameter in each instance.

Support for Java Debugger Eclipse in VisualSim.

Auto-identification for port types, primarily for plotters

Documentation upgraded with added links to video tutorials for the most commonly-used blocks

Java custom code block template

Upgrades to Existing Features

PCIe and SRIO upgraded with more statistics and increased accuracy in the algorithm

Added a Parameter_List as a Text style window to the Virtual_Machine block, which list the current hidden parameters

Documentation update for the Virtual Connection blocks in Basic Technology document

Added a rmiregistry port value in Config.Properties for the License Manager

getBlockStatus will work exactly the same as today if there is no assignment for the LHS. If there is a assignment on the LHS, then the port token will not be updated and the assignment will work.

Virtual Machine documentation has been updated to better explain the role of port_token

Added a LHS assignment for the operation of the QUEUE and TIMEQ in the Virtual Machine

Added error message to the Virtual Machine if the CALL to a sub-routine is not a Data Structure.

Modified the saving mechanism so that the neew data is stored both in memory and on disk. This way changes are never lost.

Normalized the use of strings irrespective of the content. This ensured that the behavior will always be the same, irrespective of usage.

Added another level of saving to Virtual Machine that ensures the code is always updated in the XML file.

Python and a number of optional library blocks were not opening the block on machines that had a space in the Install Path. The .bat and .sh files have been updated to make sure that these blocks will open irrespective of whether there is space or not in the directory path.

Support readFile() in Expression Evaluator

Added gif/png support for model and plotter view in Explorer

Split the Getting Started document into Installation Guide and the Getting Started document. Also added more details for troubleshooting and examples

Added over 20 videos on the use of different library blocks and methodology applications

Support for Auto Queue/TIMEQ, Event Queue sizing

Number_of_Events and Number_of_Queues have been made to Auto size

Added documentation in the tutorial for using a Eclipse debugger in VisualSim for new Java block development

readFile in Virtual Machine parameter can support relative path

Added support for a field of a data structure to be data structure

Plot attributes can be defined as parameters

Added browse ability for Instantiate Entity

Support for Autocast between double, integer and long

Recent Files added

Made "Pause" more responsive in models that complete very fast or have very few events

Model does not freeze when the simulation is executing and the user tries to perform an action. All actions are saved until after the simulation has completed.

The Instantiate Entity remembers the last opened directory

All statistics blocks support the use of parameters for the Min and Max values. Also the Batch_Count can now be 1.

Instantiate Entity works when the Class and directory name are the same

Fixed the issue where an unsaved model does not display the content of the Text_Display.

Check for parameter on the LHS of a expression in the Virtual Machine.

Added support for cache and DRAM to use the Routing Table information and the A_Hop.

Modified Qualtity-shared block for dimension to start at 1, using data structures for statistics, and priority is also 1 based.

All events are checked to make sure they are sent out at a future time.

Processor, Bus and Network Nodes now add any required fields that are not included in the incoming data structure.

The incoming data structure to the Processor only requires the A_Destination, A_Priority and A_Instruction. All other fields are optional.

Enable I_O block to use Long data type for Address.

MatLab has been tested for Visual Studio 2013 aand MatLab r2010. A script for the compile is included in /bin directory.

All Plotters now have a General data type on the input port. This eliminates the need to change conencted device port type.

Release Notes for 1310

Block Diagram Editor

Find/Search of the library block list in the folder
Find/search in the Model
Folder Tree can directly open the instance of the Hierarchical block
Drag-n-drop a Hierarchical block from the Folder Tree
Export to png, gif and html for model
Export to png, gif and html for plots
Export to Clipboard for plots
Import library directly in UserLibrary
Error highlights the hierarchical block down to the root block
Error in port type highlights the connected ports
Triangle in the Menu Bar to open the level above
Listing of Recent Files opened and Saved
Shared folder no longer available. Consolidated with the UserLibrary
Instantiate Entity has a File Chooser button
Pause works with Animation
Set Breakpoints can now be turned off when the simulation pauses at the block
DigitalDebugger and Virtual Machine debugging will display the current simulation time on the status bar at the bottom left for every pause.
Save Block in Bookmarks is now Save Block in Library
Corrected spelling error in Listen to Simulator
Updated links in the Architect Index page to the New Mirabilis Design Website
Removed the File menu in the Virtual Machine script Editor. On close, pop-up will ask to "apply" or "discard changes".
Added support for relative paths for the Virtual Machine script location
In Virtual_Machine, Virtual_Machine_Untimed and Smart_Controller blocks, the Listen to Block will display the address of each script line
Virtual_Machine, Virtual_Machine_Untimed and Smart_Controller has a Block_Path parameter that can be used to uniquely name the block.
RegEx calculations can be performed in the RHS of the Optional_Parameters in the Virtual_Machine, Virtual_Machine_Untimed and Smart_Controller
Added VS_Model_Library as the default location to host all user library, XML classes and documentation
Mouse wheel support provided for the model block diagram editor
Fixed problem with opening the Python script
Expression Evaluator can read a text file
Export to HTML packages all the required content for viewing and simulating in the browser
Export to Web creates a image within a html page
Hidden parameters of the Virtual_Machine, Virtual_Machine_Untimed and Smart_Controller have been provided in a single parameter list
Added support for Eclipse debugging of custom java block. Details available in chapter 5.
Added an icon for generating png outputs from plots from within Explorer

New Blocks, RegEx and Model Templates

Auto library containing flexray, CAN and Autosar components

Usage templates for the Auto library

Monitor bock to provide list/plot of transactions

Demo example for Monitor block

New array search RegEx functions-Find, circularFind, search and searchCircular

New Data Structure search functions-setFields, getFields, removeFields, missingFields to allow processing of several fields simultaneously.

GUI operation RegEx- myWarning, myQuestion

Added support for autosizing of all the internal queus and events for all the blocks using them.

Removed the Maximum number of queues and events in the VirtualMachine, VirtualMachineUntimed and SmartController

Added a new data type called data_struct or data_structure for use as embedded data structure in the data structure template

Support upto 32 levels of embedded data structures

Completely update virtual machine, array RegEx and data structure Rex documentation

Added a new Classes and Library tutorial

Support for BREAK keword in SWITCH/CASE expressionsVirtual_Machine, Virtual_Machine_Untimed and Smart_Controller

Virtual_Machine, Virtual_Machine_Untimed and Smart_Controller: Single Cycle, Breakpoint allows user to List Memories? (all block level memories) for each statement. In addition each Run/Resume will execute 10 statements.

Virtual_Machine, Virtual_Machine_Untimed and Smart_Controller: Add_Scheduler_Times_to_DS parameter set to true enables all statistics

Virtual_Machine, Virtual_Machine_Untimed and Smart_Controller: Port_Order_Array parameter allows user to set the order of processing for transactions arriving at the same time at multiple input ports

Bug Fixes

Force saving of XML file when the Virtual Machine has been modified

Support for strings and quotation marks

Keywords cannot be used as string arguments in the TIMEQ and QUEUE blocks

Removed extra simulator port event in custom Java blocks with more than one input.

Instruction trace at bottom of while loop, was GTO, not BCH (branch) for Virtual Machine, Virtual Machine Untimed and Smart controller

Processor block plotting: event processing

Scheduler_SW and Scheduler_HW: Order of execution fixed for Power_Manager cycles

Pipeline_All_Ports_Fast and VM_Processor instances: Updated to support INT + FP execution units

AXI Bus mode: Updated to support cache miss from slave

irand(n) and irand(n) repeated the same values more often than permitted when created new each time in a small loop

Listen to Simulator display of the Digital Run and Summary of the digitalDebugger now supports 80 characters, instead of 48

Updated documentation for Node and the ParameterSet blocks

Release Notes for 1230

Upgrades

Modified getBlockStatus to be consistent over all blocks and for all the usage forms.
Added support for array, copy.fieldname for all the operating blocks in getBlockStatus.
Application Interface block now supports blocking and non-blocking modes. The code can start excuting from where the function stopped to get data or add a delay in the VisualSim model.
Added support for SRIO for over 100 nodes for the channels between node.
Updated Processor for return from DMA and external schedulers
Enhanced the Scheduler blocks for support when the first transaction arrives at time 0.0
Updated PCIe to support channels and a number of new features
Added demonstration exampe for the dicrete optimizer. Those that are interested in the block, please contact Mirabilis Design Technical Support..

Demonstration

Release Notes for 1210

Bug Fixes, Improvements

Display, TimedPlotter, XYPlotter, DS_Timed_Plotter, DS_XYPlotter, Histogram file paths were updated to support URI for file path. This includes support for http format.

Added -path support to the Batch Mode Simulation for saving the summary file to a named directory.

Updated the Spacewire blocks to support flow control, jitter and error checking.

Added delay support for the central switch for the Serial Rapid IO block. Also added dynamic voltage change and ability to shutdown multiple links.

Network blocks were updated to support improved routing algorithm called A* using a distance plus cost heuristic function. This improves on the original Dijkstra routing algorithm with improved performance.

DS_Timed_Plotter improvements to trace field versus legend color assignments.

DS_XYPlotter improvements to legend color assignments.

Processor block updated to allow for tabs (\t) in the Processor_Setup window, annotate a REJECT field on the reject_out port, added support for N instructions per cycle ending properly in some scenarios.

DRAM improvements for refresh scenarios.

Counter blocks simplified operation to make them more intuitive.

Resource_FCFS blocks improved the utilization mean calculation timing points.

Resource_QS_Allocate blocks improved the statistics to include Quantity_Used_Min, Quantity_Used_Mean, Quantity_Used_StDev, Quantity_Used_Max to common queue statistics.

Updated Processor block to support 100% Register hit access.

Removed the Blocking Switch and replaced with the Switch and a Blocking Mechanism parameter.

Added support for setting the folder to save the batch mode summary output to a specific file.

Support for dynamic frequency change in processor

New statistics for the processor block

Support for ++ and -- in Virtual Machine

PCIe upgraded for credit policy, overhead and 8 Master and 8 Slave channels.

Html Exporter

This is an automation of the documentation output from VisualSim. The generated files can be loaded onto Explorer for viewing and simulation from within a Web Browser.

Html Exporter

This is an automation of the documentation output from VisualSim. The generated files can be loaded onto Explorer for viewing and simulation from within a Web Browser.

Channel Blocks

Channel_N block updated with a parameter to designate the channel number.
Channel_Basic, Channel_N blocks now support getBlockStatus functions: length, array of busy channels, copy of data structure, take of data structure, and statistics. getBlockStatus (Block_Name, "length") typical format.
Improved DEBUG messages to make them simpler, easier to understand.
Improved statistics so they are more consistent, easier to understand: Number_Entered, Number_Exited, Number_Rejected, Occupancy_Min, Occupancy_Mean, Occupancy_StDev, Occupancy_Max, Total_Delay_Min, Total_Delay_Mean, Total_Delay_StDev, Total_Delay_Max.

Power Library

Added new power library blocks- Power_Genertor, Power_Traffic, App_Database, Mech_Database, Resources_Modal_FSMs, Execute, Clk_ISR, Latency_Plot, Reports.
Ability to create a power-oriented model with pre-defined blocks.
User can utilize a standard FSM with states for standby, suspend, off, active, and init (startup). User inputs suspend timer in seconds, off timer in seconds, standby transitions cycles, suspend transition cycles, and off transition cycles.

RegEx

Added ability to extract array of record tokens with a single field record token using array function MyArray.common(SingleFieldRecordToken).

Token.random() functions now use the same functionality as RegEx random functions.

String.check() now checks for virtual references, memory references, or parameter references.

RecordToken.check(FieldName) returns true if the data structure contains the field name. This is identical function as RecordToken.containsRecordTokenLabel(FieldName).

Array.clear() will clear an array of strings with "" for each element.

Support for special math functions in the Virtual machine, Virtual_Machine_Untimed and Smart_Controller.

Demonstration Systems

Demonstrations systems for networking
Demonstration systems for power

Documentation

Provided a detailed list of error messages for the License Server debugging
New Chapter on file formats in the different blocks

Release Notes for 1030

Bug Fixes

Processing block has a unique ID for each instance in the model
Removed blank opening Block Diagram window
Removed debugging output to the command line for models containing C++ and SystemC blocks
Eliminated the need for "dos2unix" and "chmod +x" during installation on Unix
SystemC template now supports both hardware and system modeling methodology
Included user compile instructions for the MatLab interface

New Library Blocks

ARINC 664
ARINC 653- RTOS
Serial Rapid IO with support for all possible topologies
Serial Switch
Spacewire
Channel_N

Current Block Enhancements

Created new test methodology and test cases for all of the major library blocks (75)
Smart_Timed_Resource: Added array for time field in the SLOT mode. Every SLOT can have a different time duration
Added instruction profile output for the Virtual Machine
Support for Virtual Machine debugging and pause within a Loop
Support for profile in Virtual Machine
Added error message when simulation time exceeded the time resolution
Relative and absolute file path format has been made consistent in UNIX and Windows for Database, Reader, Writers, Traffic and Power_Manager blocks
Added multi-instruction and multi-processor support for the Listen-to-Pipeline for the Processor block
Scheduler_HW now supports transition cycles used by the power manager
Scheduler_HW also support external RegEx processing through the output port
Power_Manager, Database and Traffic blocks support Parameter and RegEx operations for initial value of the rows
Smart_Timed_Resource now supports power for each channel
Speed of SystemC improved by elimination of debug overhead in the template
Made sure that the SystemC time resolution did not cause multiple event overhead

GUI, Installer, Infrastructure, License and Simulator

Round all simulation time accuracy to time resolution
New Look and Fell for the Block Diagram Editor, Dialog Windows and Plotters
Added Scrollbar and limited the size of Parameter window
Improved the performance of GUI response time

Demonstration Systems

Computer Model
Models for using Serial Rapid IO
Spacewire example model
AFDX demonstration model
Demonstration model for ARINC 653
Digital Audio Broadcast
FPGA and Board-level model
Software task methodology has a power version
Switched ethernet model
Updated Nehalem processor models for simplified input trace file
Model of a multi-board system using FPGAs.
Model to demonstrate the profile feature of the Virtual Machine
Example models for all the Stats blocks

Documentation

Created table in Basic Technology document to map system modeling requirements to appropriate library blocks
Added documentation for all the support string functions
Added examples for all regEx functions
Updated documentation for new installer
New training material supporting all the new fucntionality and methodology
Tutorials have been simplified with more diagrams and less narration
Updated SystemC tutorials to support all variations of timed communication between SystemC and VisualSim

Release Notes for 1020

Bug Fixes

Simulator was generating events on variable rounding values of the simulator
Cycle_Accurate_Cache was not prefetching properly for L2, L3 levels.
Memory_Controller was not processing multiple burst transactions correctly.
Fixed BasicQueue, PriorityQueue searching for E-14 time resolution events.
Simulator was scheduling multiple statistics events at end of simulation.
Eliminated a source of memory leak because of the simulator queue building up the queue depth without clearing out finished items. Now there is no memory leak even for models running 10 days

Cache/Memory/DRAM

Support for intelligent prefetching, meaning not prefetching an address already being prefetched or a miss in progress.
Improved cache associativity processing to array manipulation instead of looping through each associative address to improve performance.
Improved DEBUG messages to make them simpler, easier to understand.
Improved statistics so they are more consistent, easier to understand.
Improved timing of cycle accurate clocks.
Removed dependency on A_Task_ID field internally.
Least Recently Used (LRU) now supports N Way Associativity.
Support for Next_Memory_Bus (true) separating request and miss/prefetch on separate busses.
Validated Read, Write, Read/Write, Write/Read burst model timing against RTL implementations.
Support for fragmenter entering the Memory_Controller (MC) based on BL and memory width.
MC Fragmenter returns incoming Event_Name after fragmentation complete.
MC Fragmenter generates a new Event_Name to Command Queue.
Increased the performance of the MC by improving the array processing functions, see RegEx Arrays.
Improved the MC clock alignment using IEEEremainder function.
Created standalone model, named Memory_Controller_Tracer, to transform the MC DEBUG text information into detailed plots containing tRAS, tRP, tRCD, Read Sequential, Write Sequential, Read_Cycles, Write_Cycles, tRL, tWL, etc.
Created standalone model, named Compare_Monitor_Files, to trace transactions entering exiting MC + HW_DRAM.
Reduced number of Threads generated in HW_DRAM by 8 to improve performance.

Library

Added new library blocks- VCD_Writer, Cycle_accurate_Cache, Rapid IO Node, SpaceWire Node, Link, Core, Switch Ethernet, Application Interface, Database, CORBA
Added power support for all queues of the Smart_Timed_Resource
Timing Diagram blocks supports DRAM, AXI and Memory Controller plotting
Cache and Memory statistics are now long values to support large number of requests beyond 4 billion
DS_xTime_yData and DS_xData_yData support Save/view and are linked to the Post Processor
Added support for all UNIX versions in the APplication Interface block
Created a new infrastructure to generate cache request traces for application code.
Added Qemu environment to the VisualSIm package for running virtual OS on 6 different processors- SH4, MIPS, ARM, ARM Cortex, Intel x86, SPARC and Intel x86_64
Added conolidated statistics generation for the Android SDK tool

GUI, Installer, Infrastructure, License and Simulator

New fully merged single installer for Post Processor, Architect and License Manager
Updated Install Website with complete documentation available
Improved simulator processing of cycle accurate models to consistently convert simulator time as a double value into an internal long representation based on the timeResolution of the Digital simulator.
Added the initialization time to the command line out
Added the number of events for each sub-block
Reduced the time lookup overhead for multi-domain simulations
Eliminated overhead for port width search at run-time
Virtual_Machine, Smart_Controller blocks updated to improve event processing for cycle accurate models by maintaining the order of internal threads generated at the same clock resolution. In addition, events generated by WAIT(), TIMEQ() functions maintain the same time resolution, order for clock timed events.
Improved simulator performance for cycle accurate models.

RegEx

Added new functions for obtaining common values and indices of arrays.

Added standard functions into tokens

Support for empty array in extract function

Support all Java string functions

Added new update Power RegEx for the Smart_Timed_Resouce

Demonstration Systems

Demonstrations systems for important RegEx functions
Models of the Xeon, Opteron, Cevatek and Nehalem processors
Models for system scheduling, licensing management and cluster organization
Demonstration system for the Application Interface block
Demonstration examples for the basic modeling blocks such as clocks, events, viewers etc.
New demonstration for the Rapid IO, Spacewire, Memory Controller and Cycle Accurate Cache
New flow control model with explanation
Hardware and software methodology models
Android Model with CORBA interface to the Android SDK
Models to demonstrate Database and CORBA blocks
Models for Virtual Channels and Network-on-Chip
Model for Bank Teller, Reliability and Functional Analysis
Power models for SoC
Demonstration for the Colt distribution functions
New demonstrations for usage and power modeling of the Scheduler_HW, Scheduler_SW and Smart_Timed_Resource

Documentation

Memory Controller + HW_DRAM documentation now includes timing diagrams, more detailed explanation.
Newer version installer for all products
Documentation for the Processor, VCD_Writer, Cycle_Accurate-Cache, Memory_Controller, HW_DRAM, Rapid IO, Spacewire
Updated examples for all regEx functions
Added RegEx string operator page
New examples for applications in Getting Started document
Updated Basic Technology document
Documentation for the Switched Ethernet
Many template models have explanation in the body of the model
More explanation to the library block templates
New organization of all the demonstration models according to the library structure
New organization of all application templates according to usage
Search engine covers all parts of the application

Release Notes for 930

Error in power manager average power and cumulative power for each device. Fixed.

Add a new field to the power manager for both the blocks and the total to hold the average.

Updated clock, pulse, ramp for the new Time class

Bug Fixes

IN Block inside a hierarchical block now generates an event to guarantee continued processing.
Cache, DRAM, Processor, IO blocks updated for parameter consistency.
DS_While block updated for a looping issue.
Register_Expr_N, Register_N updated for parameter consistency.
DS_Timed_Plotter, DS_XYPlotter, HistogramPlotter, TimedPlotter, XYPlotter updated for consistent parameter usage.
Schedulers, Resource_*, Queue_* blocks updated for common statistics.
FSM director block updated for operation with Digital Only simulator.
Support for arrays in memory init for single value
Virtual Machine- Open Block will open a file if the script is in a text file
Parameters cannot be used on the LHS of a expression
Removed over 40 Null Pointer Exceptions

AHB/AXI/Linear Bus

Support for address pipeline in AHB Bus
Adding extra cycle to any transaction in AHB Bus
Defining variable number of cycles for Split and Retry operation in AHB Bus
Support for memory variable (boolean value) to initiate Retry in AHB Bus. Current support was only for Cache and DRAM blocks.
Simplified custom flow RegEx functions for Linear Bus. Reduce the number of variables and consolidated some functions
Support for sending first or last word for the AHB and Linear Bus
AXI bus supports single and dual request channel
Support for text file script to define custom arbitration AXI Bus
Accelerated the AXI bus by over 10X
Added event-based acknowledge for both Master and Slave side for AXI Bus
New utilization statistics for the AXI Bus
Support sending first or last word for the AXI Bus

Memory Controller/ HW_DRAM

Support for custom arbiter in text file for memory controller
Added 4 more scenarios for latency in HW_DRAM
Support event-based acknowledgement for Bus interface
Support for multiple independent Banks
Support for Bank switching time- t_rrd
Provide greater visibility to the type of operation by defining the operation in the memory controller. These include Read_Sequential, Read_Non_Sequential etc.
Added t_DQSS to each write
HW_DRAM computes the processing time
Support for writing to actual memory. Commented out but user can add to their flow.
Modified code for traceability.

SystemC

Support for SystemC 2.2 on Linux
Support for TLM 2.0 on Linux
Add a initiator template block to the library
Added a tutorial for TLM
Added a new TLM example for integration of VisualSim standard library and TLM blocks
Added Debug resolution to determine the amount execution details printed to command-line
Added functions to eliminate the struct definition for the input and output ports

GUI, Installer, Infrastructure, License and Simulator

Added Toolbar item for easy jump to the next-level (Up) of a hierarchical block
Modified icons of the Virtual Machine and Hierarchical blocks to be UML compatible
Added support for images in icons using the Custom Icon Editor
FSM now contains Final State
Post Processor now support FlexLM
Command-line simulator writes simulation execution report to a file on success, failure, time spent and memory consumed.
Command-line execution catches error messages and writes to report file
Added write to file for Block listener for the Virtual Machine, Virtual Machine Untimed and Smart Controller
Added a profiler to Virtual Machine, Virtual Machine Untimed and Smart Controller to view the time allocated, number of times executed and total time allocated.
New installer than consolidates the License Manager, Architect and Post Processor
Step-by-step instructions for installer
Support for standalone library custom code destination
New blocks to support CORBA and Database drivers
Display and Display_Fast support Save to File to option
Added setup of Display, Display, DS_xTime_yData and DS_xData_yData blocks to the PostProcessor
Reorganized Languages and interfaces into separate directory section for easier access
Script has been moved one-level higher
Block with the error is now highlighted

RegEx

Added new functions for single and multi-level array processing.

Functions for handling events and clocks. This is different from a simple delay.

Event-based RegEx

Clock-based Events

Timed-based events

Random number generators

Added standard functions into tokens for faster execution

Demonstration Systems

New demo for event-based traffic generators
Examples for Split and checking remote destination memory for Retry in AHB
Retry example for Linear AHB
Added example for single core and multi-core architecture exploration for Android
Model of the Intel 4-core Nehalam processor
Updated Dynamic Instantiate example system
Examples for all the RegEx functions available

Documentation

Exception messages in Processing, Decision blocks improved.
Cache, DRAM, Processor, IO blocks Exception messages updated for consistent format.
New Getting Started Document
New video training including Introduction to VisualSim- video of the class lecture
New video training for using the SystemC TLM block
Updated Basic Technology document
Updated AHB Bus block documentation
Detailed information on internal operation and using events for the AXI Bus
New front page and model pages
Added index and search for the Block, RegEx and Tutorial documentation
Better organization and recommended flows for documentation
Video tutorials for the installation
Front page can be access from Help->About.
Single installer for all products

Release Notes for 910

Release 3

DS_xTime_yData now supports TNow in the RegEx

Power_Manager will not have any transition cycles if the Enable_Transition_Cycles is disabled.

Parameter name cannot be used as a block memory name in the Virtual Machine

Automatic cast from RHS to LHS has been reduced to only the standard list in the RegEx section of the Basic Technology Document

New videos of the Installation of Architect, Explorer, Post Processor and License Manager

SystemC TLM block support native SystemC TLM import

Release 2

New installer that supports automatic reference for FlexLM
Expanded the number of keywords for the Search Engine
Basic Technology contains a number of new sections
Mobile license facility for FlexLM
New demonstrations for the RegEx functions
RegEx functions are now included in the Block Documentations ection for easy access and search
Smart_Resources now support default for not using Priority field
New DS_To_Excel block supports write to file, column headers and formating
Removed local language support for the installer
Removed separate test for the Java JDK in installer
Added separators between user input in installer
Added radio buttons for selecting the License Manager
Now concatenations of names can support N number of strings and parameters
RegEx- write_to_file- Removed spaces at end
RegEx- appendFile- Removed spaces at end
Linear Bus and AHB Bus support Round-Robin arbitration
Video description of Opening a modeling, running a model and constructing the first model
Documentation supports FlexLM licensing
Batch mode simulation has a print-out to a text file at the end of each simulation. The text file will be in the $VS install directory.

License Manager

VisualSim now supports FlexLM as a licensing options. The current support is for Sparc Solaris 64-bit Operating System for the License Server.

Simulator

Accelerated scalar and arrays tokens with embedded methods for improved search and retrieval during simulation
Support for events

Graphical User Interface

Added Find and Replace for all Text Editors
Fixed the Full Screen to not replicate the toolbar for every selection
Added enhance debugging for the Virutal Machine

Libraries

New Library called Memory. Library is located in Hardware_Modeling.

New block: Memory_Controller

New Block: HW_Cache

New Block: HW_DRAM

New Block: AXI_Flow_Control

New Block: Custom_CPP

Timing Diagram: Added AXI and Memory Controller

AXI- Added timing diagram with multiple colors

AXI- Enhanced the flow control to be built-in and no longer require a bridge.

AXI- Support for first or last word out

AXI- Added output queues

AXI- Support Request-Acknowledge mode for the Traffic Generator and AXI Bus

AHB Bus: Supports output for last word

Linear Controller: Support for first word only

Linear Controller: AHB mode checkbox is now a separate block

RegEx Functions: checkField

RegEx Functions: readAllVirtual

RegEx Functions: checkAssertion

RegEx Functions: setValue in scalar tokens

Events: New features for trigger activity without wires and clocks functions.

RegEx Functions: newEvent

RegEx Functions: Event

RegEx Functions: WAIT for event in the Virtual Machine, Smart Controller

Events: New features for trigger activity without wires and clocks functions.

RegEx Functions: Array.append

RegEx Function: containsRecordTokenLabel to data structure

Virtual Machine: Support both global and local virtual connection

Virtual Machine: Supports breakpoint on address

Demonstration Systems

Added demo models for the HW Cache, Memory Controller, AXI Flow Control, Processor to write buffer, HW DRAM models.
Add new demos for RegEx functions- readAllVirtual, setValue and checkAssertion

Documentation

Created a new block documentation listing with search and index.
All block documentation has been updated to a new consistent format
All block documentation are associated with a demo model to explain the features
Block documentation has direct reference to the detailed documentation
Basic technology in a new format with more content
RegEx has examples and format information
Tutorials have been updated with more explanations
All error messages now follow a standard format with a error, short description, error code and resolution suggestions.
New Tutorials format. All tutorials are combined into one book.
Getting Started and Tool introduction are in Video.
New documentation for the AXI, AHB and Linear Bus
Class Notes have been updated for the new libraries and contains flow diagrams for all the Hardware blocks.

Release Notes for 830

Special Note

Some of your models may open with errors and not run correctly. The stats_in and stats_out ports of the Scheduler_SW, Scheduler_HW, Smart_Resource and Smart_Controllers have been removed. This will not affect the operation of the model. You will need to manually go in and edit the models for the following:

Remove the stats_in and stats_out port if it still exists in the model. To do this, Right-click on the block->Configure->Port. The two ports will be at the bootm of the list. Select the name and click on Remove.
To get the statistics for these blocks, use the new Resource_Statistics_Report bloc located in Performance_Modeling->Results or Full_Library->Results->Statistics_Generator.

The Soft_Gen block has been updated. You will need to manualy update this block in your existing models. You need to do two things.

Remove the two parameters- Number_Instruction_Type and Processor_Speed_Mhz. To do this, open the parameter window and click on Remove. Select the parameter, one at a time.
Right-click on the block and select "Open Instance". Remove the block in the model titled uEngine_Script.

The statistics for the Smart_Resource, TimedQueue, EventQueue and Schedulers have now been consolidated to have the same set of fields. Any models you have that uses these fields may need to be adjusted to the new field names.

Libraries

Resource_Statistics_Report: Central location to generate/reset statistics for all the Schedulers, Smart_Resource and Smart_Timed_Resource a model. This block can be customized for the user needs.

Smart_Timed_Resource: New block in Smart_Resource Folder and available as a standard upgrade. This can be used as a Timed version of the Smart_Resource with an extra option of SLOT scheduling.

PCIe: Available now as a library element in the Folder. Look in Hardware->Emerging_Bus->PCIe_bus

AXI: Available now as a library element in the Folder. Look in Hardware->Emerging_Bus_Standards->AXI_Bus.

Bridge: Updated to be full fledged block and located in Hardware->Bus_Switch_Ctrl Folder. Check the example in Pre-Built_Models->Using Hardware Architecture Blocks

Switch: Updated to be full fledged block and located in Hardware->Bus_Switch_Ctrl Folder. Check the example in Pre-Built_Models->Using Hardware Architecture Blocks

Blocking_Switch: Updated to be full fledged block and located in Hardware->Bus_Switch_Ctrl Folder. Check the example in Pre-Built_Models->Using Hardware Architecture Blocks

RegEx "Virtual_Machine" and "Smart_Controller" adds script support for SWITCH, CASE, CALL, RETURN to increase functionality, reduce script size, improve performance over multiple if, else-if, else statements.

RegEx "Virtual_Machine" and "Smart_Controller" adds ability to reference file for script, and save reference file, parsed file. Improves performance for large models.

RegEx adds the ability to directly select an array element or array index randomly.

RegEx adds the ability to directly increment or decrement an interger, long, or double.

RegEx adds the ability to directly generate a random number from an integer, long, or double.

SoftGen instruction generator adds selection, random, or continuous loop selection. Debug mode added for large task lists.

AXI Bus Architectural Model adds user access to internal master, slave transaction arrays, including an external throttle control mechanism. User can select either Round Robin or Fixed Priority for each Slave port. User can alter the Fixed Priority order of Master port processing. Support for multiple AXI Bus layers added. Master and Slave thresholds can be set for each port. AXI Bus ships with eight master ports, four slave ports and can be easily expanded to 12 master ports, 6 slave ports. Debug mode added to trace transtions in and out of ports.

PCIe Bus updated for easier extension

Queues, Timed Queues, Schedulers, Virtual Machines now support a common statistics data structure.

Demonstration Systems

Added AXI, PCIe Bus demonstration models.
Using Hardware Architecture blocks