VCDWriter
Hardware Setup / VCDWriter
Block Name: VCDWriter
Code File Location: VisualSim/actor/arch/trace/VCD_Writer
This block is used to create a vcd file of the signals in the model. The block takes in a data structure on the input, notes the arrival time and generates the appropriate vcd file items. The incoming data structure can contain multiple fields that need to be written. Unlike the vcd write in Verilog, this block will write out the values even if the value has not changed. The file can be read by any waveform viewer. The current version does not support data structure write out.
In current HDL-based design flow, we usually use the HDL simulator to run the simulation. Based on the simulation results, we will do a lot of analysis to verify the correctness of the designs. For the convenience of post simulation analysis, we may dump all signals’ value changes into the dump file and check them later after simulation is finished. Because the simulation time for a huge design is very long, we may only dump a part of signals instead of all signals to reduce the simulation time and the size of the dump file. However, if we are going to check a signal which doesn’t exist in the dump file, we have to include this signal in the dumpling list and re-run the simulation again, which requires a long simulation again. In this situation, if we know the value of the checked signal can be calculated from other existing signals in the dump file, we can directly calculate the value changes of this signal according to the existing records in the dump file to avoid a new simulation run. Therefore, an efficient tool that can perform efficient evaluations from a signal expression would be very useful for post simulation analysis.
The target of this problem is to develop an efficient tool that can evaluate given signal expressions from existing records in the given dump file. For example, given a Verilog expression “a = b & c”, you have to read the value changes of signals “b” and “c” from the given dump file, evaluate all the value changes of signal “a”, and output these value changes into a new dump file. It should be noted that a legal Verilog expression can be very complex. There are a lot of different operators in Verilog syntax which can be combined to form a complex expression. Those signals appear at both left-hand-side and right-hand-side of the expression can be single-bit or multiple-bit (i.e. bit-vector). The logic values of all signals can be “0”, “1”, “X”, and “Z”. You may have to develop an efficient parser for reading the given expression first. Furthermore, because the format of the dump files are also defined clearly in the Verilog standard, which is called the VCD (value change dump) file format, you also have to develop a parser to understand the dump file and prepare the output file that is compatible to the VCD standard.
Parameter Name |
Value (Data Type) |
Explanation |
File_Name |
"t1.vcd"(String) |
This is the file name to save the vcd content. The format is "first.vcd". " are required around the name. |
File_Path |
Windows: "file:/C:/VisualSim/" UNIX: "file:/usr/Apps" (String) |
This uses the standard file URL parameter. In Windows, it will be "file:/C:/VisualSim/" and on UNIX, it will be "file:/usr/Apps" |
Time_Resolution |
"ms" /* ns,ms,us,s,ps */ |
This is the time resolution in the Verilog side and is the setting for this vcd file. The options are ns, ms, us, s and ps. |
Start_Time |
1.0e-5 (double) |
Time at which to start collecting data |
End_Time |
1.0e-3 (double) |
Time at which to stop collecting data |
List_of_Input_Port_Field_names |
{"Bytes","Clock","Priority","Delay"} |
This is a array of strings. Each string is a field name. There can be any number of fields names in this list. Each is assigned a identified in the vcd file. |
List_of_Variable_name |
{"total_bytes","clk","pri","dly"} |
This is an array of strings. The length of this array must match the Input_Port_Field_Name array. This is the corresponding names to be listed in the vcd file that the Verilog will understand. The waveform viewer will identify each signal using the variable name and not the field name. |
List_of_Data_Types |
{"reg","reg","wire","real"} (Array of Strings) |
This is an array of strings. The length of this array must match the Input_Port_Field_Name array. This is the corresponding data type to be listed in the vcd file that the Verilog will understand. The available options are wire, reg, real and integer. |
Port Name |
Type |
Explanation |
input |
data structure |
input port requiring a data structure containing fields to be written to file. |
Created with the Personal Edition of HelpNDoc: Single source CHM, PDF, DOC and HTML Help creation