CycleAccurateCache

Hardware_Modeling/Cache
Block Name: Cycle_Accurate_Cache

Code File Location: VisualSim/actor/arch/Memory/Cycle_Accurate_Cache

Description

The Cycle Accurate Cache is a cycle accurate cache model that performs many standard cache operations. The size of the cache determines the functional hit ratio, based
on actual requests. The Cache_Name, Next_Higher_Memory_Name, Architecture_Name, Cache_Size_KB, Cache_Speed_Mhz, Cache_Bytes_per_Word, Cache_Line_Words, Cache_N_Associativity, Cache _Replacement_Policy, Cache_Write_Policy, Cache_Prefetch_Lines, Bus_Width_Bytes, DRAM_Name, Overhead_Cycles, First_Word_Flag, Snooping_Flag, Sim_Time, and DEBUG are cycle accurate cache parameters.

An incoming transaction will check that the field A_Destination matches the Cycle_Accurate_Cache block, or the field A_Destination equals the Architecture_Name (hello message), else a model level exception will be thrown. The Cycle_Accurate_Cache processes incoming transactions for port "to_cache":

Number_Entered    = Number_Entered + 1
   if (!port_token.containsRecordTokenLabel("A_Line")) { // New Data Request
   GTO (Process_New_Data_Request)
}
else             {           // Read or Write Cmd
   GTO (Process_Data_Request)
}

    The Cycle_Accurate_Cache processes returning miss transactions from the port "fm_next_cache":

    GTO (Process_Miss_Return) // Read or Write Cmd

The Cycle_Accurate_Cache processes returning prefetch transactions from the port "fm_next_cache":

    Line_Idx         = Prefetch_Arr.search(port_token.A_Line, 0)
    if (Line_Idx   != -1) {
        Prefetch_Arr = Prefetch_Arr.removeElement(Line_Idx)
   }
    else                   {
     throwMyException(Block_Name_ + " detected an unknown Prefetch Address (" + port_token.A_Address + "))
     }
     GTO (Process_Prefetch_Return)

How to use the Cycle_Accurate_Cache in a model:

    (1) Set the Cycle_Accurate_Cache block parameters according to cache name, size, width, etc.
    Make sure the Next_Higher_Memory, DRAM_Name are set to a valid Memory_Controller + HW_DRAM name.

    (2) Add a Transaction Source block generating Processor_DS data structures.
    Data_Structure_Name: "Processor_DS"

    (3) Add a Processing block after the Transaction Source block to set the following fields, according to destination, request transaction size:
    A_Destination (DRAM_Name), A_Bytes (64, for example), A_Bytes_Remaining (0), A_Bytes_Sent (64, for example)

(4) Add Memory_Controller + HW_DRAM blocks, set parameters.
Make sure the Next_Higher_Memory, DRAM_Name are set to a valid Memory_Controller + HW_DRAM name.

(5) Test the Cycle_Accurate_Cache by enabling DEBUG set to true, and add a Display block to the stats output.
Does the DEBUG output look like transactions are being processed correctly?

Parameter	Explanation	Example
Cache_Name	Name of this cache block. This is an unique name for this block and cannot be duplicated with any schedule, Virtual Machine or other hardware blocks.. This name is used in the Routing Table.	"Cache_1"
Next_Higher_Memory_Name	This is the next level memory and can either be a DRAM, Cache, Cycle_Accurate_Cache, HW_DRAM or a full custom block.	"SDRAM_1"
Architecture_Name	Name of the Architecture_setup block that this is associated with.	"Architecture_1"
Cache_Size_KB	Size of Cycle_Accurate_Cache in KBytes	32
Cache_Speed_Mhz	Speed of Cycle_Accurate_Cache in Mhz	500.0
Cache_Bytes_per_Word	The number of Bytes per Word in the Cycle_Accurate_Cache	8
Cache_Line_Words	The number of Words based on Cache_Bytes_per_Word in a single Cache Line	8
Cache_N_Associativity	N_Way associativity 1, 2, 4, 8, 16, 32 only.	4
Cache_Replacement_Policy	The value can be Least_Recently_Used, Most_Recently_Used or None. If None, this feature is disabled.	"Least_Recently_Used" /* Least_Recently_Used, Most_Recently_Used, None */
Cache_Write_Policy	This parameter can be Write_Through, Write_Back or None. If None, this feature is disabled.	"Write_Back" /* Write_Back, Write_Through, None */
Cache_Prefetch_Lines	The number of cache prefetch lines based on Cache_Line_Words parameter. A value of 0 disables the feature.	1 /* 0,1,2,3 */
Bus_Width_Bytes	Width of the Bus that this cache block is interfaced too	16
DRAM_Name	Name of attached DRAM device, used internally to determine if L1,L2,L3 caches exist in the model.	"SDRAM_1"
Overhead_Cycles	Overhead cycles added to Word or Line request. Cache overhead cycles could be an internal pipeline, for example.	1
Next_Memory_Bus	Enables separate bus for miss, prefetches.	false
First_Word_Flag	Determines when transaction is sent, on first or last word of response.	false
Snooping_Flag	Enables cache coherency, not activated in script.	false
Read_File	Custom Cache Algorithm for the model.	"none"
Number_Statistics_Samples	Number of statistics samples for the model.	1.0E-05
SimTime	This links the simulator end period within this block to the top-level simulation period.	1.0E-05
DEBUG	If the DEBUG messages are to be sent to the status port, then the value is a Boolean true, else false.	false

Port	Explanation
to_cache	This is the West Side input port. This block can be connected to two buses, one on either side. This is connected to the processor.
fm_cache	This is the West Side output port. This block can be connected to two buses, one on either side. This is connected to the processor.
stats	Debug messages and statistics are output on this port.
to_next_cache	This is the East Side output port. This block can be connected to two buses, one on either side. This is connected to the lower level memory.
fm_next_cache	This is the East Side input port. This block can be connected to two buses, one on either side. This is connected to the lower level memory.

Created with the Personal Edition of HelpNDoc: Easily create EBooks