CoreConnect_PLB
Full Library / Hardware_Modeling / Standard_Bus / CoreConnect_PLB
Block Name: CoreConnect_PLB
The Processor Local Bus (PLB) protocol is a high performance bus for interconnecting processor, memory subsystems, and high bandwidth peripherals. There are IBM and Xilinx versions of the bus that match specific timing for reads and writes. The CoreConnect Bus hierarchical block supports four master and two slave ports with bi-directional ports.
Parameter |
Explanation |
Example |
Architecture_Name |
This is the name of the Architectue_Setup block. |
"Architecture_1" |
Bus_Name |
The Bus_Name must be unique with the Architecture_Name, which can be thought of as the platform domain. |
“Bus_1” |
Architecture_Bus_Name |
Name of the Architecture_Bus block. |
Architecture_Name + "_" + Bus_Name |
CoreConnect_Speed_Mhz |
Bus Speed. |
1000.0 |
Burst_Size_Bytes |
It represents the CoreConnect Bus model ability to fragment large transactions into smaller transactions at a master or slave. |
64 |
FIFO_Buffers |
It is the amount of buffering at the master or slave, based on the Burst_Size_Bytes of the largest bus fragment. |
32 |
Request_Clock_Multiplier |
It modifies the request response rate from the master to slave and slave to master. A Request_Clock_Multiplier of 0.99 represents one clock time per request transfer from master to slave port, or visa versa. |
0.99 |
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