FPGA for SoC design verification
System-on-chip (SoC) integration stands behind the success of the semiconductor industry to continue to meet its goals for better, smaller, and faster chips. Multifarious tools are used for the design and verification of electronic systems. Verification is one the most important aspects, as it demonstrates the functional correctness of a design. Using FPGA to verify the SoC design is a powerful tool and is becoming a very important part of semiconductor design.
Traditional methodologies are not sufficient to fully verify a system. There is a compelling reason to do dynamic timing analysis. EDA vendors provide solutions for basic simulation that adequately support low-density devices. These tools are not powerful enough to debug and verify to the extent that is required by designers of today to meet the cutthroat competition in meeting schedules and debugging effectively in large-scale FPGAs.
A few architecture exploration tools resolve the issues related to verification by reusing the system model to test the timing, power, and functionality based on real-time and realistic workloads. They address the multitude of drawbacks in the current verification solutions. We will discuss addressing each particular issue and how each one was resolved.
Problems behind current SoC verification
With the increases in size and complexity of SoCs, there is a growing need for more effective verification tools. Excessive competition is shrinking time-to-market requirements. This makes it difficult for designers to use the traditional approach of implement-and-test designs in hardware.
Functional simulation tests only the functional capabilities of RTL design. What they essentially do is send a generic set of inputs, and they test for those scenarios and determine whether it worked or not. It fails to provide timing, power consumption, and responses to workloads from the rest of the system.
Static analysis fails to find problems that can be seen when the design is run dynamically. Timing analysis methodology also has various drawbacks. In a real system, dynamic factors can cause timing violations on the SoC. It can tell the user whether the design can meet setup and whether the applied timing constraints are met. One example is in the design of time-sensitive network routers, in which care must be taken to specify the priority levels that could use the time slots. Care must also be taken so that a priority level packet doesn’t use the resources allocated for another time slot. For instance, control data frames are of Priority Level 3. In the current time slot, Class A packets start using resources. While Class A frames are being transferred, the next time slot initiates and the packets scheduled during this new time slot (control data frames) have to wait until the current transfer gets completed. Static analysis tools will never be able to find this problem. Similarly, with packet routing through a common crossbar in a network, packets could end up getting dropped. So proper flow control mechanism should be in place. Static timing analysis will not be able to find this problem.
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