The 2 most important considerations while designing a product are- Throughput and latency, as well as the scalability or the ease of re-designing in case of need.
The ARM Corelink CMN-600 enables the latest SoC’s to offer unmatched data throughput and the lowest edge to cloud latency in the market. The combination of performance and efficiency provided by the third-generation CoreLink coherent backplane products advances the Intelligent Flexible Cloud by enabling efficient compute capability at any point from the edge of the network to the cloud.
Optimized with the latest ARM Cortex®- A processors, CoreLink CMN-600 is the industry’s only complete coherent backplane IP solution for the ARMv8-A architecture. Designers and system architects can scale high-performance SoC designs from 1 to 128 Cortex-A CPUs (32 clusters) with native ARM AMBA® 5 CHI interfaces, the industry standard specification for high-performance on-chip communication.
The CoreLink CMN-600, is designed for an intelligent connected systems across a wide range of applications including but not limited to networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The most notable highlights of them are:
• Build more powerful infrastructure SoCs from edge to cloud.
• 5x throughput uplift compared to today’s solution.
• Coherent mesh interconnects with integrated agile system cache
Interestingly, when I was going through VisualSim Architect, an efficient simulation and modelling tool, it had techniques to ramp up the processor and CoreLink performance. Also, it is very feasible during the later stages to make any changes, if needed, at the system level. This CMN -600 has used the AMBA 5 CHI specification along with 1 to 96 IO interfaces. CoreLink CMN-600 coherent multichip links (CML) provide the capability of extending the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, enabling system designers to attach more compute or acceleration with a shared virtual memory.