ARM vs RISC-V Cores | System level Comparison-Latency, Power

Aug 16, 2024 | Author : admin_mirabilis

August 16, 2024September 5, 2024 admin_mirabilis Leave a comment Blog

Methodology for System-level Comparison of ARM vs RISC-V Cores for Latency and Power Consumption System-level analysis is the only methodology to compare the performance and power consumption of two processor architectures. Unfortunately, processor models to perform the comparison are not easily available. This article describes a performance and power comparison methodology using system-level IP between […]

Hardware Software Partitioning- Simulations and Discussions

Aug 16, 2024 | Author : admin_mirabilis

August 16, 2024September 5, 2024 admin_mirabilis Leave a comment Blog

Hardware Software Partitioning – Simulations & Discussions Hardware/software partitioning is the concept of dividing an application’s computations into a part that executes sequential instructions on a microprocessor (the “software”) and a part that runs parallel circuits on some IC fabric like an ASIC or FPGA (the “hardware”), such as to achieve design goals set for […]

Functional Safety for Braking System through ISO 26262

Aug 08, 2024 | Author : admin_mirabilis

August 8, 2024September 5, 2024 admin_mirabilis Leave a comment Blog

Functional Safety for Braking System through ISO 26262, Operating System Security and DO 254 Implementation of safety measures is on the rise in today’s automotive world in order to minimize the hazards in case of system malfunction. Today’s automobiles run various safety critical applications like ABS, electronic power steering, air bag sensors, radar sensing, and […]

Switch Design for Optimal Service Quality

Jul 26, 2024 | Author : admin_mirabilis

July 26, 2024July 26, 2024 admin_mirabilis Leave a comment Blog

Switch Design for Optimal Service Quality A large number of current-generation switches and routers operate in a multi-protocol, non-blocking, packet segmentation, packet reassembly, parallel execution environment. The system must support quality of service (QOS) levels that take into account video frame rate constraints, switch-to-switch throttling control, packet priorities, error checking/correction, and retransmission of overflow packets […]

Design UCIe-based Multi-die SoC with VisualSim