Ways to improve the system level model implementation

Feb 18, 2016 | Author : Deepak Shankar

February 18, 2016September 11, 2023 Deepak Shankar Blog

In each and every project, system engineers and hardware/software architects face the issues like correlation between a system level model and RTL, striving to achieve fidelity in system level model and the accuracy of the actual implementation. The actual problem lies not in implementation, but on how to assemble the models. In this blog, we […]

Linking System-level modeling to RTL and Source code

Oct 10, 2015 | Author : Deepak Shankar

October 10, 2015September 25, 2023 Deepak Shankar Blog

Everyone is always looking for this elusive link from high-level conceptual design to implementation. Also, what is high-level and what is implementation also depends on the team charter. Is it a functional model or timing or a power model? Is the implementation in RTL (Verilog or VHDL) or C, C++ or Java for software? Or […]

System-level Models- How well do they correlate with the implementation?

Oct 10, 2015 | Author : Deepak Shankar

October 10, 2015 Deepak Shankar Blog

System engineers and hardware/software architects are always worried about the correlation between a system-level model and RTL. Also, can a system-level model achieve the fidelity and accuracy of the actual implementation. We at Mirabilis Design, have evolved a methodology that allows the user to create a design flow that incorporates all the checks and balances […]

Helping create the Right Design

Ways to improve the system level model implementation

Linking System-level modeling to RTL and Source code

System-level Models- How well do they correlate with the implementation?

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