Hardware Software Partitioning- Simulations and Discussions

Aug 16, 2024  |  Author : admin_mirabilis

Hardware Software Partitioning – Simulations & Discussions Hardware/software partitioning is the concept of dividing an application’s computations into a part that executes sequential instructions on a microprocessor (the “software”) and a part that runs parallel circuits on some IC fabric like an ASIC or FPGA (the “hardware”), such as to achieve design goals set for […]

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Functional Safety for Braking System through ISO 26262

Aug 08, 2024  |  Author : admin_mirabilis

Functional Safety for Braking System through ISO 26262, Operating System Security and DO 254 Implementation of safety measures is on the rise in today’s automotive world in order to minimize the hazards in case of system malfunction. Today’s automobiles run various safety critical applications like ABS, electronic power steering, air bag sensors, radar sensing, and […]

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Reducing Power Consumption | Early System-Level Modeling

Aug 08, 2024  |  Author : admin_mirabilis

Measuring and Reducing Power Consumption Using Early System-Level Power Modeling Power evaluation in the early stages of the product design has been performed mostly using analytical methods such as spreadsheets. These spreadsheets typically contain the power for different tasks or devices and the sheet adds the worst case or the average of the power.  These […]

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Switch Design for Optimal Service Quality

Jul 26, 2024  |  Author : admin_mirabilis

Switch Design for Optimal Service Quality A large number of current-generation switches and routers operate in a multi-protocol, non-blocking, packet segmentation, packet reassembly, parallel execution environment.  The system must support quality of service (QOS) levels that take into account video frame rate constraints, switch-to-switch throttling control, packet priorities, error checking/correction, and retransmission of overflow packets […]

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Design UCIe-based Multi-die SoC with VisualSim

Jul 26, 2024  |  Author : admin_mirabilis

Architecture-stage EDA Tool VisualSim to Design UCIe-based Multi-die SoC While performance is the key factor for commercial success of any semiconductor chip, the development cost and time plays an even more critical role in the successful launch of the chip. Extremely complex and expensive semiconductor fabrication technologies such as nano-sheet FETs are used today at […]

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