Architecture Exploration of ARM-based SoC and Chiplets

Mar 15, 2025  |  Author : admin_mirabilis
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Unlocking Optimal Power and Performance: A Deep Dive into ARM SoC Modeling In the competitive world of semiconductor design, balancing power consumption with high performance is a constant challenge. With VisualSim Architect, engineers can simulate intricate ARM-based SoCs with unparalleled accuracy, paving the way for innovative, power-efficient solutions. The Future of SoC Design: As the […]

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New System-Level IP Library for Cadence Tensilica Processors

Feb 20, 2025  |  Author : admin_mirabilis
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Mirabilis Design Accelerates SoC Development with New System-Level IP Library for Cadence Tensilica Processors Mirabilis Design Inc., a leader in system-level IP and simulation solutions, has unveiled a new IP library tailored for Cadence Tensilica processors. This strategic development aims to significantly accelerate System-on-Chip (SoC) design and development processes, offering designers a robust platform for […]

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Arteris FlexNoC and Ncore Network-on-Chip IPs

Feb 17, 2025  |  Author : admin_mirabilis
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Mirabilis Design Adds System-Level Modelling Support for Industry-Standard Arteris FlexNoC and Ncore Network-on-Chip IPs Mirabilis Design Inc., a leader in system-level modeling and simulation solutions, has announced the integration of support for Arteris FlexNoC and Ncore Network-on-Chip (NoC) IPs into its VisualSim Architect tool. This advancement enables designers to perform early-stage architectural exploration and performance […]

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What is Architectural Queueing?

Feb 10, 2025  |  Author : admin_mirabilis
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What is Architectural Queueing? Architectural queueing is an important topic in the sense that queues are needed at the system-level. Queueing theory has been a mathematical concept since the late 1800’s; actually Agner Erlang from Copenhagen, Denmark; https://en.wikipedia.org/wiki/Erlang_distribution; who worked in the telephone industry; developed the first queues!  Architectural queueing handles port operations; whether a […]

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Webinar on Multi-Core Scheduling – Register Today!

Feb 10, 2025  |  Author : admin_mirabilis
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Software scheduling across multi-core architecture with Coherent Caches and Distributed Computing Systems Transform Your Approach to Multi-Core Scheduling with Mirabilis Design As multi-core systems evolve, so do the challenges in software scheduling. Engineers and architects are constantly seeking ways to reduce latency, enhance throughput, and manage power more efficiently. If you’re looking to stay ahead […]

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