SPARC & LEON

Flexible pipeline structure for designing space and missile application

Other Processor Families

  • RISC-V
    Parameterized RISC-V models for MIMD and SIMD
  • PowerPC
    Over 10 different processor families
  • Coldfire
    Applications for using Coldfire in medical and automotive
  • Nvidia Drive-PX
    Models integrated with CAN-FD for ADAS system design
  • SPARC and LEON
    Flexible pipeline structure for designing space and missile application
  • Intel
    Server, desktop and ATOM processor model
  • AMD
    Server and GPU models
  • Marvell
    Implementation of the PXA320 for architecture analysis of embedded system design

Quick Explanation

  • 32-bit processor
  • Sparc v8 architecture
  • 7-stage pipeline
  • Hardware multiply, divide and MAC units
  • IEEE-754 FPU support
  • Symmetric Multi-processor support
  • Supports 2 cache execution units
  • Supports AMBA-AHB bus interface
  • Power management
  • Up to 1 GHz

Protocol

  • Evaluate use of Leon in space-based applications
  • Size cache and clock speeds for your application
  • Evaluate available throughput for scalability in space for over-the-air deployment

Model Link

SPARC - Implements 4-Stage Pipelined SPARC Dhrystone Model