Right Design Decisions with Early System Exploration

Creating a new System-on-Chip (SoC) for streaming video with a MPEG application requires a number of decisions to be made before development is scheduled. The design would have some amount of existing hardware and software components in the SoC. The new application such as H.264 application will have some known and mostly unknown characteristics. These decisions must be evaluated at the product definition phase.

Examples of these analyses will include:

1. Will my current processor support the addition of the new application?
2. If I need to upgrade do I need to move to the next generation processor or do I use dual processor architecture?
3. If I use dual processor architecture, what will be the possible bottlenecks- processor stalls, low hit-ratio or excessive bus utilization?
4. What is the size and frequency of all the peripherals?
5. Do I need to add a MPEG co-processor that synchronizes the ARM Pipeline, or should use hardware acceleration only for the motion estimation?
6. What happens to my performance if I increase the number of concurrent threads from 3 to 8?
7. What is the power consumed by the MPEG co-processor?

These questions can be answered with the help of modeling and simulation of complete Streaming board considering both hardware and software parts of the system. Architecture exploration and performance analysis with SystemC takes huge amount of time, graphical modeling and simulation tools such as VisualSim can reduce the overall time spent on model development and allows user to explore system architecture better. In VisualSim, the architecture is constructed using only the parameterized building blocks available in the VisualSim library. The processor models are either provided by Mirabilis Design or constructed by the user using the Processor Modeling Toolkit. A standard or custom processor can be constructed in about 3-6 hours with validation following that. The other hardware structures and the RTOS will be constructed by instantiating a block, making the connecting and updating parameter values. Custom switches and bus matrix can be created hierarchically using the scheduler and VisualSim library blocks.

If software exists, this can be imported into the model as an instruction stream. If it does not exist, then the behavior can be constructed using the library blocks. Creating a function to target hardware can be easily done using the scheduler, discrete component blocks and the expression language.

The software can be statically scheduled to a particular processor. Alternately, it can be dynamically scheduled based on criteria such as processor loading or utilization. These decisions can be setup to view the automatically generated statistics. If the performance is insufficient and the motion estimation needs to be targeted as hardware, the same model can be modified to run as a hardware block.

VisualSim eliminates considerable effort required in creating detailed C or SystemC models before making the partitioning decisions ca. For a large SoC, the entire model has been constructed in 3 weeks and analysis complete in an additional one month. Once decisions are made, then the hardware can be modeled in SystemC and the software in C. A performance or statistical model constructed using VisualSim can give 80% accuracy in a shorter time period and with sufficient detail to address the bottleneck question. Models built to answer specific questions such as memory controller bottlenecks can be completed in a day or two.