R4

Multi-Core 5G baseband SoC processor

ARM Processor

  • Cortex M0 Microcontrollers
    Architecture model of the energy efficient Arm micro-controllers
  • Cortex M3 Microcontrollers
    Architecture model of the energy efficient Arm micro-controllers
  • Cortex M4 Microcontrollers
    Architecture model of the energy efficient Arm micro-controllers
  • A7
    power-performance model
  • A8
    Highly-optimized for performance and power efficiency
  • A9
    32-bit processor core
  • A53
    Enables Multi-Core power efficient ARMv8 processor
  • A72
    Enables Multi-Core high performance 64-bit ARMv8 processor
  • R4
    Multi-Core 5G baseband SoC processor

Quick Explanation

  • Experiment with the latency and power impacts on safety critical applications
  • Separate I- and D- cache from 4 to 64 KB
  • Eight-stage dual-issue pipeline
  • Instruction pre-fetch, mispredict/flush and selected dual-issue execution
  • Concurrent execution for load-store, MAC, shift-ALU, divide and floating point
  • 64-bit AMBA AXI bus master for Level-2 memory and peripheral access
  • Supports DMA arbitration

Protocol

  • ARM Cortex-R is a f32-bit RISC core, optimized for hard real-time and safety-critical applications. Implements the ARM Real-time (R) profile

Model Link

e405 Platform Model using ARM R4