Bus to connect hardware discrete components on a board. Used to evaluate the latency impact.
VisualSim PCI and PCIx library provide designers with the ability that enables them to design complex computing process and validate the architecture of their proposed system. This library block is an exact implementation of the PCI bus standard 3.0 from PCI SIG. Allied standards such as Compact PCI and Industrial PCI technologies are also supported. This library covers the functionality of the protocol, arbiters, performance timing (internal and the periphery) and power. These blocks can be combined with other elements from the VisualSim extensive library including bridges, crossbar, memories, AXI and PCIe.
PCI and PCIx library contains a number of standard parameters for easy configuring of protocol options, has a large associated library of traffic pattern generators, and statistics. The traffic can be trace-based, statistical and processor-driven. The statistics including read/write latency, buffer occupancy at the ports, utilization, throughput, data transfer per Master and per Slave, and activity report per port. The library block support Round-Robin, First come-First Serve, Priority-Pre-emption and custom. The PCI bus block can be used as an interconnect between high bandwidth peripherals closer to the CPU for performance gains. This model has been fully validated against the specifications.
VisualSim PCI and PCIx library supports all the standard features of the protocols like bus widths, and clock speeds, and can run millions of transactions in seconds. The library block is a transaction-level model and can be used for trace-based simulation or emulation of the complete board. The library has complete compatibility with different processors, IOs and memories to be interfaced with the PCI/PCIx. The introduction of Split transaction allows for the models to demonstrate the higher performance options by preventing retry of currently busy slaves. The library can be used for designing the PCI/PCIx intellectual property in a SoC, a standard chip on a board or to integrate with FPGAs. The modelling environment can be used to design large aerospace system, real-time industrial designs and multi-board computers.
PCI or Peripheral Component Interconnect uses a shared bus topology to allow for communication among the different devices on the bus ie..the different PCI devices are attached to the same bus , and share the bandwidth. It can run at clock speeds of 33 or 64 Mhz. At 32 bits and 33 Mhz, it will throughput rate of 133 Mbps. PCIx stands for PCI Extended. The PCIx spec essentially doubled the bus width from 32 bits to 64 bits, thereby increasing bandwidth.