NOC

Generic, CMN600, AMD Infinity and other vendor brands

Semiconductor buses

  • AMBA
    Support AMBA 1-5
  • CoreConnect
    IBM and Xilinx version supported for use as internal memory. Also support 60X bus
  • I2C
    Synchronous, multi-master, multi-slave, packet switched, single-ended, serial computer bus
  • NoC
    Generic, CMN600, AMD Infinity and other vendor brands

Quick Explanation

  • Used to model the SoC and size the interfaces, flits, clock speeds, buffers and VLANs
  • Define the protocol and routing table
  • Evaluate power management
  • Evaluate the topology to minimize latency and maximize throughput
  • Evaluate the topology to minimize latency and maximize throughput

Protocol

  • Configurable to use to create proprietary and commerical NoC
  • Used to configurable the NoC and to compare feasibility with traditional Bus and mesh topology.

Model Link

Network-on-Chip (NoC)

VisualSim provides the first industry-strength simulator, Network-on-Chip (NoC) to simulate standard technology from Arteris and ARM CMN, and proprietary technology at semiconductor and Intellectual Property companies. Different abstraction levels are required for topology assessment versus timing diagram correctness. This library generates models that are extremely fast and can simulate millions of packets. VisualSim Network-on-Chip is fully integrated on a chip through interconnect networks that can serve the communication demands among the different components of the system. This library can span synchronous and asynchronous clock domains, and un-clocked asynchronous logic.

NoC is a new paradigm for SoC design. Increasing integration produces a situation where bus structure, which is commonly used in SoC, becomes blocked and increased capacitance poses physical problems. In NoC architecture traditional bus structure is replaced with a network which is a lotsimilar to the Internet. Data communications between segments of chip are packetized and transferred through the network. The network consists of wires and routers. Processors, memories and other IP-blocks (intellectual property) are connected to routers. A routing algorithm plays a significant role on networks operation. Routers make the routing decisions based on the routing algorithm.

Parameters

The library can be used to optimize the SoC for a better trade-off in area and power, and be able to compare the architectures with traditional bus and peer-to-peer connections. At the same time NoC requires a thorough design process including topology selection and mapping, link planning, routing, packet size, and buffer allocation. The integration with the hardware, networking and performance libraries of VisualSim enables the designer to assemble a complete System-on-Chip (SoC), in a matter of days. These can include memories, processor, DSP, hardware engines, DMA and I/O. In addition, the library of buses and other networking protocols are used to integrate with existing bus-based sub-systems that might exist on the same SoC.

Features

  • The Network-on-Chip (NoC) library provides the flexibility to construct the model at statistical and signal-accurate detail, for rapid design, optimization and Quality of Service (QoS) assurance.
  • The library contains an open networking routing architecture that can be customized for wormhole-type to a full-blown TCP modelling.
  • The library provides an extensive analysis reports that includes buffer allocation, throughput, end-to-end latency for read and write, queue occupancy, effective utilization of connected devices, and graphical outputs

In General

Network-on-Chip(NoC) is a new paradigm to make the interconnections inside a system-on-chip(SoC) system. In traditional solutions, interconnections were realized using a bus structure. In NoC technology the bus structure is replaced with a network which is a lot similar to the internet.

NoC- Implements Cache coherency mechanism