New System-Level IP Library for Cadence Tensilica Processors

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Mirabilis Design Accelerates SoC Development with New System-Level IP Library for Cadence Tensilica Processors

Mirabilis Design Inc., a leader in system-level IP and simulation solutions, has unveiled a new IP library tailored for Cadence Tensilica processors. This strategic development aims to significantly accelerate System-on-Chip (SoC) design and development processes, offering designers a robust platform for early architecture exploration and performance validation.

Key Features of the New System-Level IP Library for Cadence Tensilica Processors:

  • Comprehensive Processor Support: The library encompasses a wide range of cycle-accurate models for processors, including ARM, RISC-V, and Tensilica, as well as AI accelerators and GPUs. This extensive support enables designers to simulate and validate diverse processing elements within their SoC designs.

  • Customizable Memory Controllers: Designers have the flexibility to configure memory controllers, DRAM, and DMA components, facilitating precise modeling of memory hierarchies and data flow within the system.

  • Advanced Interconnect and Interface Modeling: The library includes detailed models for interconnects, interfaces, and network protocols, allowing for accurate simulation of data communication and system integration aspects.

  • Application-Specific Workloads: A rich set of application-specific workloads and algorithms are provided, enabling designers to assess system performance under realistic operating conditions and tailor optimizations accordingly.

Benefits of Integrating the IP Library into SoC Development:

  • Accelerated Development Cycles: By leveraging pre-validated models and simulation capabilities, designers can reduce development time by up to 20%, expediting time-to-market for new products.

  • Cost Efficiency: The ability to identify and address design issues early in the development process can lead to a 40% reduction in production costs, minimizing costly iterations and rework.

  • Scalability for Complex Architectures: The library supports the modeling of architectures with over 1000 cores, providing scalability for high-performance computing applications and complex SoC designs.

 

This initiative by Mirabilis Design aligns with the industry’s shift towards system-level design methodologies, addressing the growing complexity of modern SoCs. By offering a comprehensive and customizable IP library, Mirabilis Design empowers engineers to explore architectural trade-offs, optimize performance, and achieve efficient design closure.

 

For more detailed information on this development, please refer to the official press release here:  https://www.einpresswire.com/article/784970482/mirabilis-design-accelerates-soc-development-with-new-system-level-ip-library-for-cadence-tensilica-processors