Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing & power constraints

This Webinar will enable FPGA users to accelerate the adoption of a new generation of heterogeneous FPGA platforms through high level application mapping software.

Webinar Details:

Date: Wednesday, October 11, 2023

Join at : 9:00 AM PST | 12:00 PM EST

Alternatively, at: 4:30 PM Japan/Korea, 3:30 PM China, 1:30 PM India, 10 AM CEST

During this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.

VisualSim Architect has a large library of system-level modeling components that are used to assemble the Versal hardware model. Using the innovative behavior-to-architecture mapping technology, individual signal processing tasks are mapped to the heterogeneous resources of processor, logic and AI Engine Tiles. The mapped model is simulated for various use-cases, workloads, Versal variations and requirements. Using this approach, the design can evaluate the expected performance-power prior to design entry. This solution augments current AMD tooling by adding an exploration layer on top.

The methodology will be demonstrated for signal processing applications but the same can be applied to other applications, as well. The user can conduct trade studies of how different implementations and mappings change system performance and identify potential bottlenecks. The high-level application can be captured using models of key application building blocks and a fast application exploration to heterogeneous hardware targets.

VisualSim uses stochastic models to focus on early application mapping exploration to heterogeneous SoC compute resources. System architects responsible for high-level complex system mapping, not design entry, can easily focus on performance and ability to conduct rapid design iteration. This solution extends the current FPGA toolkits with a new pre-design-entry focused on application analysis. This analysis uses fast simulation and easily configurable models without the need for the software code or RTL. This approach provides guidance to down-stream sub-system (AIE, PL, PS) design entry development teams.

Takeaways:

You will learn to optimize the use of the AMD-Xilinx Versal FPGAs. They will be exposed to a methodology that enables trade-offs without the need for C++ or RTL code. This will enable the design team to integrate the systems engineering requirements flow with the design entry.

In addition, you will learn how the Processor, Logic Elements and AIE/Tensor are interconnected using Network-on-Chip- NoC (Horizontal and Vertical).

What is the latency when using the NoC vs direct interface to go between Logic->AIE or Processor and the AIE?
How does different data cache size requirements affect the utilization of the AIE Tile network?
How does different mapping decisions affect the throughput of the application?
What is the maximum input data that can be processed?

VisualSim Architect is a modeling and simulation platform for the rapid trade-off and exploration of the application mapping on the heterogeneous resources of the FPGA architecture. With the advent of AIE and Tensor units on FPGAs, the mapping of signal processing algorithms on FPGAs is challenging. Each option requires a different interconnect between the logic implementation of various tasks and the HBM/DDR memory. For example, is it better to implement function 1 on the Logic and use the direct interface to send data to the AIE for function 2 or is it better to use the NoC interface to store the data in HBM before sending a processing request to the AIE.

Are there trade-offs between higher throughput vs lower latency? What does this do for the efficient use of the AIE/Tensor tile network? How does the power consumption change between implementations? What role can the processor play to control operations or execute variable sized data functions.

During this webinar, Mirabilis will show how reusable modular components can enable the rapid modeling and architecture evaluation of FPGAs for an application such as beamforming radar or SDR. VisualSim is a system design platform for the architecture exploration of systems, software and silicon. VisualSim provides a large library of System-level IP components that are used to assemble the FPGA resources such as processor cores, logic, AI tiles, tensor units and Network-on-Chip. The IP block contains power, performance, and functional definitions, thus enabling a true architecture trade-off study.

The Webinar will use the pre-built models of the FPGA to try different mapping and partitioning options for various data sizes, algorithm types and use-cases. The example considered will be a beam-forming Radar and map the individual functions to Logic Elements and AIE/Tensor. Regression experiments will try different mappings and interconnect between the logic elements and between logic and the AIE/Tensor. We will look at latency, throughput, bottleneck detection and maximizing the utilization of the FPGA.

System design can optimize, test, and validate the performance and power consumptions of systems prior to development. Mirabilis Design will demonstrate how VisualSim Architect can be used to quickly create an architecture, map the application tasks onto the available resources, and conduct regression simulation to identify the optimal solution that meets the requirements. VisualSim system design can partition the application across one and more FPGAs.

Want to know more? Register for the Webinar today!

Date: Wednesday, October 11, 2023

Join at : 9:00 AM PST | 12:00 PM EST

Alternatively, at: 4:30 PM Japan/Korea, 3:30 PM China, 1:30 PM India, 10 AM CEST

System Simulation, Architecture Exploration, Power Management, Performance Analysis

Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing & power constraints

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