Task Generator

Generates a stream of instructions based on a profile of an application

Generating_Synthetic_Instructions

Browsable image of the model.

  • For an executable version,
  • Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
  • To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.
Generating_Synthetic_Instructionsmodel <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0.0</td><td>0.0</td></tr><tr><td>Value_1</td><td>1.0</td><td>1.0</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>ARM9_Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual.  \\n</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual.  \\n</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;ARM_INSTR&quot;</td><td>&quot;ARM_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n   Mnew Ra  Rb  Rc  Rd Re Rf  Rg Rh;   /* Label */\\n   ARM  EXEC             ; /* one execution unit */\\n   EXEC INT_1                ; /* ARM execution unit  */\\n\\nbegin INT_1                  ;\\n   MV_MOV 1 4                ; /* group MOVE */\\n   MV_MVN 1 4                ;\\n   MV_MRS 1 2                ;\\n   MV_MSR 3                  ;\\n\\n   ART_ADD 1 4               ; /* group ARITHMETIC */\\n   ART_ADC 1 4               ;\\n   ART_SUB 1 4               ;\\n   ART_SBC 1 4               ;\\n   ART_RSB 1 4               ;\\n   ART_RSC 1 4               ;\\n   ART_MUL 2 3               ;\\n   ART_MLA 2 3               ;\\n   ART_MULS 4                ;\\n   ART_MLAS 4                ;\\n   ART_UMULL 3 4             ;\\n   ART_UMLAL 3 4             ;\\n   ART_SMULL 3 4             ;\\n   ART_SMLAL 3 4             ;\\n   ART_UMULLS 5              ;\\n   ART_UMLALS 5              ;\\n   ART_SMULLS 5              ;\\n   ART_SMLALS 5              ;\\n   ART_CMP 1 4               ;\\n   ART_CMN 1 4               ;\\n   ART_QADD 1 2              ;\\n   ART_QSUB 1 2              ;\\n   ART_SMULXY 1              ;\\n   ART_SMULAXY 2             ;\\n   ART_SMULWX 1              ;\\n   ART_SMULAWX 2             ;\\n   ART_SMULALX 2 3           ;\\n   ART_CLZ 1                 ;\\n\\n   LGL_TST 1 4               ; /* group LOGICAL */\\n   LGL_TEQ 1 4               ;\\n   LGL_AND 1 4               ;\\n   LGL_EOR 1 4               ;\\n   LGL_ORR 1 4               ;\\n   LGL_BIC 1 4               ;\\n\\n   *BR_B 3                    ; /* group LOGICAL */\\n   BR_BL 3                   ; \\n   BR_BX 3                   ;\\n   BR_BLX 3                  ;\\n\\n   #LD_LDR 1 5               ; /* group LOAD */\\n   LD_LDRT 1 5               ; \\n   LD_LDRB 1 5               ; \\n   LD_LDRBT 1 5              ; \\n   LD_LDRSB 1 5              ; \\n   LD_LDRH 1 5               ; \\n   LD_LDRSH 1 5              ; \\n   LD_LDM_PC 5               ; \\n   LD_LDM 1 12               ; /* number of registers */\\n\\n   STR_STR 1                 ; /* group STORE */\\n   STR_STRT 1                ; \\n   STR_STRB 1                ; \\n   STR_STRBT 1               ; \\n   STR_STRH 1                ;\t\\n   STR_STM_PC 1 2            ;\\n   STR_STM 1 12              ; /* number of registers */\\n\\n   MISC_SWP 3                ; /* group MISCELLANEOUS */\\n   MISC_SWI 3                ; \\n   MISC_BKPT 3               ; \\n\\nend   INT_1                   ;</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n   Mnew Ra  Rb  Rc  Rd Re Rf  Rg Rh;   /* Label */\\n   ARM  EXEC             ; /* one execution unit */\\n   EXEC INT_1                ; /* ARM execution unit  */\\n\\nbegin INT_1                  ;\\n   MV_MOV 1 4                ; /* group MOVE */\\n   MV_MVN 1 4                ;\\n   MV_MRS 1 2                ;\\n   MV_MSR 3                  ;\\n\\n   ART_ADD 1 4               ; /* group ARITHMETIC */\\n   ART_ADC 1 4               ;\\n   ART_SUB 1 4               ;\\n   ART_SBC 1 4               ;\\n   ART_RSB 1 4               ;\\n   ART_RSC 1 4               ;\\n   ART_MUL 2 3               ;\\n   ART_MLA 2 3               ;\\n   ART_MULS 4                ;\\n   ART_MLAS 4                ;\\n   ART_UMULL 3 4             ;\\n   ART_UMLAL 3 4             ;\\n   ART_SMULL 3 4             ;\\n   ART_SMLAL 3 4             ;\\n   ART_UMULLS 5              ;\\n   ART_UMLALS 5              ;\\n   ART_SMULLS 5              ;\\n   ART_SMLALS 5              ;\\n   ART_CMP 1 4               ;\\n   ART_CMN 1 4               ;\\n   ART_QADD 1 2              ;\\n   ART_QSUB 1 2              ;\\n   ART_SMULXY 1              ;\\n   ART_SMULAXY 2             ;\\n   ART_SMULWX 1              ;\\n   ART_SMULAWX 2             ;\\n   ART_SMULALX 2 3           ;\\n   ART_CLZ 1                 ;\\n\\n   LGL_TST 1 4               ; /* group LOGICAL */\\n   LGL_TEQ 1 4               ;\\n   LGL_AND 1 4               ;\\n   LGL_EOR 1 4               ;\\n   LGL_ORR 1 4               ;\\n   LGL_BIC 1 4               ;\\n\\n   *BR_B 3                    ; /* group LOGICAL */\\n   BR_BL 3                   ; \\n   BR_BX 3                   ;\\n   BR_BLX 3                  ;\\n\\n   #LD_LDR 1 5               ; /* group LOAD */\\n   LD_LDRT 1 5               ; \\n   LD_LDRB 1 5               ; \\n   LD_LDRBT 1 5              ; \\n   LD_LDRSB 1 5              ; \\n   LD_LDRH 1 5               ; \\n   LD_LDRSH 1 5              ; \\n   LD_LDM_PC 5               ; \\n   LD_LDM 1 12               ; /* number of registers */\\n\\n   STR_STR 1                 ; /* group STORE */\\n   STR_STRT 1                ; \\n   STR_STRB 1                ; \\n   STR_STRBT 1               ; \\n   STR_STRH 1                ;\t\\n   STR_STM_PC 1 2            ;\\n   STR_STM 1 12              ; /* number of registers */\\n\\n   MISC_SWP 3                ; /* group MISCELLANEOUS */\\n   MISC_SWI 3                ; \\n   MISC_BKPT 3               ; \\n\\nend   INT_1                   ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>TaskGenerator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Name</td><td>&quot;My_SoftGen&quot;</td><td>&quot;My_SoftGen&quot;</td></tr><tr><td>Mode_of_Operation</td><td>&quot;Loop&quot; /* Field gets input, Random selects a Task, Loop is sequential */</td><td>&quot;Loop&quot;</td></tr><tr><td>DEBUG</td><td>false /* To Debug Port */</td><td>false</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;TaskGenerator</td><td>ProcessorGenerator-&gt;TaskGenerator</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>4.0E-4</td></tr><tr><td>Instruction_Mix_File</td><td>Instruction_Mix_Table.txt</td><td>&quot;Instruction_Mix_Table.txt&quot;</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                  */\\n</td><td>/* First row contains Column Names.                  */\\n</td></tr><tr><td>Number_of_Samples</td><td>35</td><td>35</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;MAC_ARM9_PROC_Utilization_Pct_Min, MAC_ARM9_PROC_Utilization_Pct_Mean, MAC_ARM9_PROC_Utilization_Pct_Max, MAC_ARM9_I_1_Hit_Ratio_Mean&quot;</td><td>&quot;MAC_ARM9_PROC_Utilization_Pct_Min, MAC_ARM9_PROC_Utilization_Pct_Mean, MAC_ARM9_PROC_Utilization_Pct_Max, MAC_ARM9_I_1_Hit_Ratio_Mean&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>None</td><td>None</td></tr></table>

During system architecture exploration phase, the software code will not be available or processor models to execute code is not available or the number of boards required is too expensive. To overcome this challenge, VisualSim has a profile-based software generator. This generator takes into consideration the list of tasks and the percentage of the different types of instructions- integer, floating-point, fixed-point, load-store, move, memcopy, branch, mispredict and complex math.