Cache Memory Storage

Architecture Cache
Use of the Cache block as the L2 cache, receiving request from the I_1 and D_1 in the processor and a miss to a DRAM.
Cycle-Accurate Cache
Modeling the cycle-accurate cache with 4-way associativity and snoop flag disabled.
Cache/Memory Hierarchy
Shows an end-to-end operation with Processor core as a trace, 2 level cache, AXI bus, Memory Controller and DRAM
Architecture Memory
Use of the Cache block as the L2 cache, receiving request from the I_1 and D_1 in the processor and a miss to a DRAM.
Cycle-accurate Memory
Modeling multiple requester with addresses to DDR and LPDDR
Disk
Host computer with SATA interface to a local disk drive
Hybrid Drive
Multi-level drive with cache, SDRAM, flash and disk drive. Uses a ARM R8 for contorl processing
Flash
Evaluate flash from different memory vendors by varying standard Flash parameters
SSD
SSD using a generic Flash and a RISC-V for processing
Network-Attached Storage
Modeling a video streaming server that is stored on a redundant NAS

NAS_Server_Read_Write_v3_Nodes

Browsable image of the model.

For an executable version, the WebStart version. (Java Plug-in Required)
Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.

http://support.microsoft.com/gp/howtoscript