Bridge connects the Processor on an AHB bus to the DRAM on a PCIe Bus
Hardware Devices
Communication Channel Define a serial channel, parallel channel, FPGA-to-FPGA link, Aurora communication channel, and wireless channel with BER.
PCIe-to-AHB Bridge Bridge connects the Processor on an AHB bus to the DRAM on a PCIe Bus
AHB-to-AXI Bridge Shows a network containing a AHB connected to an AXI bus via bridge
DMA DMA is connected to Slave devices and I/O across the PCIe bus
Switch/Crossbar/Serial Switch Model shows the use of the Switch in managing connections between a large number of Masters and Slaves
UART Demonstrates the use of the UART and USART blocks in VisualSim
FPGA_Main_Board_External_Intf1
Browsable image of the model.
To download OpenWebStart
click on the links - Windows- Compatibility:Windows 10 or higher (*) macOS - Compatibility:macOS 10.15 (Catalina) or higher (*) Linux - Compatibility:Ubuntu 18.04 LTS or higher (*)
For an executable version,
Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.