PCIe-to-AHB Bridge

Bridge connects the Processor on an AHB bus to the DRAM on a PCIe Bus

FPGA_Main_Board_External_Intf1

Browsable image of the model.

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FPGA_Main_Board_External_Intf1model <h2>TextDisplay5</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;DRAM_1Wrmoni&quot;</td><td>&quot;DRAM_1Wrmoni&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>TextDisplay4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Option_read&quot;</td><td>&quot;Option_read&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Destination = &quot;DRAM_2&quot;\\ninput.A_Source = &quot;external2&quot;</td><td>input.A_Destination = &quot;DRAM_2&quot;\\ninput.A_Source = &quot;external2&quot;</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>external</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0</td><td>0</td></tr><tr><td>Value_1</td><td>1.0E-03</td><td>1.0E-3</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>ExpressionList3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Data = &quot;Main_Sensor&quot;</td><td>input.A_Data = &quot;Main_Sensor&quot;</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Data = &quot;FPGA&quot;</td><td>input.A_Data = &quot;FPGA&quot;</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>TextDisplay3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Instructions Complete&quot;</td><td>&quot;Instructions Complete&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>TextDisplay2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Instructions Complete&quot;</td><td>&quot;Instructions Complete&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Destination = &quot;MAC_ARM9&quot;\\ninput.A_Hop = &quot;MAC_ARM9&quot;\\ninput.TIME = TNow\\ninput.A_Variables = 32\\ninput.A_Source = &quot;MAC_ARM9&quot;</td><td>input.A_Destination = &quot;MAC_ARM9&quot;\\ninput.A_Hop = &quot;MAC_ARM9&quot;\\ninput.TIME = TNow\\ninput.A_Variables = 32\\ninput.A_Source = &quot;MAC_ARM9&quot;</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Detailed Processor Activity&quot;</td><td>&quot;Detailed Processor Activity&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>Proc_Preempt</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;Proc_Preempt&quot;</td><td>&quot;Proc_Preempt&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names.              */\\nParameter_Name                 Parameter_Value     \\nPath                           none     \\nRead_File                      none                \\nSave_Files                     false               \\nProfile_File                   none           \\nListen_to_File                 none                \\nDuplicate_Input                true                \\nProfile                        0                   \\nMaximum_Loops                  1000000             \\nBlock_Reference                Block_Name         \\nPort_Order_Array               {&quot;input&quot;}         \\nAdd_Scheduler_Times_to_DS      false \\nPreempt_Cycles                 100\\nBlock_Name_Tab                 Block_Name + &quot;\\t&quot; \\nPreempt_Enable_Flag            true\\nProcessor_Preempt_Time         (1.0E-06 / Processor_Speed) * Preempt_Cycles\\n</td><td>/* First row contains Column Names.              */\\nParameter_Name                 Parameter_Value     \\nPath                           none     \\nRead_File                      none                \\nSave_Files                     false               \\nProfile_File                   none           \\nListen_to_File                 none                \\nDuplicate_Input                true                \\nProfile                        0                   \\nMaximum_Loops                  1000000             \\nBlock_Reference                Block_Name         \\nPort_Order_Array               {&quot;input&quot;}         \\nAdd_Scheduler_Times_to_DS      false \\nPreempt_Cycles                 100\\nBlock_Name_Tab                 Block_Name + &quot;\\t&quot; \\nPreempt_Enable_Flag            true\\nProcessor_Preempt_Time         (1.0E-06 / Processor_Speed) * Preempt_Cycles\\n</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                */\\nSource_Node    Destination_Node   Hop           Source_Port ; \\nProcessor_1    Cache_1            Port_1        bus_out2    ;\\nCache_1        Processor_1        Port_2        output      ;\\nCache_1        SDRAM_1            Port_2        output      ;\\nSDRAM_1        Cache_1            Port_4        output      ;\\nSDRAM_1        Processor_1        Port_4        output      ;</td><td>/* First row contains Column Names.                */\\nSource_Node    Destination_Node   Hop           Source_Port ; \\nProcessor_1    Cache_1            Port_1        bus_out2    ;\\nCache_1        Processor_1        Port_2        output      ;\\nCache_1        SDRAM_1            Port_2        output      ;\\nSDRAM_1        Cache_1            Port_4        output      ;\\nSDRAM_1        Processor_1        Port_4        output      ;</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;MAC_ARM9_PROC_Utilization_Pct_Min, MAC_ARM9_PROC_Utilization_Pct_Mean, MAC_ARM9_PROC_Utilization_Pct_Max, MAC_ARM9_I_1_Hit_Ratio_Mean,Processor_1_PROC_Utilization_Pct_Min, Processor_1_PROC_Utilization_Pct_Mean, Processor_1_PROC_Utilization_Pct_Max&quot;</td><td>&quot;MAC_ARM9_PROC_Utilization_Pct_Min, MAC_ARM9_PROC_Utilization_Pct_Mean, MAC_ARM9_PROC_Utilization_Pct_Max, MAC_ARM9_I_1_Hit_Ratio_Mean,Processor_1_PROC_Utilization_Pct_Min, Processor_1_PROC_Utilization_Pct_Mean, Processor_1_PROC_Utilization_Pct_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Pipeline</td><td>Pipeline</td></tr></table> <h2>TriggeredTransaction</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Plot</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Proc_Name</td><td>&quot;MAC_ARM9&quot;</td><td>&quot;MAC_ARM9&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache&quot;</td><td>&quot;Cache&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.005</td></tr><tr><td>DRAM_Name_1</td><td>&quot;DRAM_1&quot;</td><td>&quot;DRAM_1&quot;</td></tr><tr><td>DRAM_Name_2</td><td>&quot;DRAM_2&quot;</td><td>&quot;DRAM_2&quot;</td></tr></table> <h2>IN</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Interrupt</td><td>&quot;Interrupt&quot;</td></tr><tr><td>Destination_Type</td><td>Local</td><td>Local</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>OUT4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Interrupt</td><td>&quot;Interrupt&quot;</td></tr><tr><td>Destination_Type</td><td>Local</td><td>Local</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Isolate_Input2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Isolate_Output</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>PCIe_Bus</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;PCIe_1&quot;</td><td>&quot;PCIe_1&quot;</td></tr><tr><td>Number_of_Lanes</td><td>16 /* Can be an array */</td><td>16</td></tr><tr><td>Slave_Buffer</td><td>512  /* Max Bytes @ Slave */</td><td>512</td></tr><tr><td>Master_Buffer</td><td>512  /* Max Bytes @ Master */</td><td>512</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.005</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td></tr><tr><td>Header_Bytes</td><td>16  /* 32 Bit Mode, includes CRC Bytes */</td><td>16</td></tr><tr><td>Number_of_Ports</td><td>{12, 12}  /* Master, Endpoint  Ports */</td><td>{12, 12}</td></tr><tr><td>BER</td><td>1.0E-11</td><td>1.0E-11</td></tr><tr><td>Max_Payload_Size</td><td>64  /* Write, Read Data */</td><td>64</td></tr><tr><td>Max_Payload_Req_Size</td><td>128  /* Read Requests */</td><td>128</td></tr><tr><td>PCIe_Gen_1</td><td>250.0  /* DO NOT MODIFY */</td><td>250.0</td></tr><tr><td>PCIe_Gen_2</td><td>500.0  /* DO NOT MODIFY */</td><td>500.0</td></tr><tr><td>PCIe_Gen_3</td><td>985.6  /* DO NOT MODIFY */</td><td>985.6</td></tr><tr><td>PCIe_Gen_4</td><td>1969.2  /* DO NOT MODIFY */</td><td>1969.2</td></tr><tr><td>PCIe_MBps</td><td>PCIe_Gen_2  /* Per Lane */</td><td>500.0</td></tr><tr><td>Read_to_Write_Ratio</td><td>0.5  /* 0.0 to 1.0 */</td><td>0.5</td></tr><tr><td>Devices_Attached_to_Slaves</td><td>{{&quot;DRAM_1&quot;},{&quot;Dev&quot;},{&quot;DRAM_3&quot;},{&quot;Dev_4&quot;},{&quot;Dev_5&quot;},{&quot;Dev_6&quot;},{&quot;Dev_7&quot;},{&quot;Dev_8&quot;},{&quot;Dev_9&quot;},{&quot;Dev_10&quot;},{&quot;Dev_11&quot;},{&quot;DRAM_2&quot;}}</td><td>{{&quot;DRAM_1&quot;}, {&quot;Dev&quot;}, {&quot;DRAM_3&quot;}, {&quot;Dev_4&quot;}, {&quot;Dev_5&quot;}, {&quot;Dev_6&quot;}, {&quot;Dev_7&quot;}, {&quot;Dev_8&quot;}, {&quot;Dev_9&quot;}, {&quot;Dev_10&quot;}, {&quot;Dev_11&quot;}, {&quot;DRAM_2&quot;}}</td></tr><tr><td>Root_Complex_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Endpoint_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Enable_Plots</td><td>true</td><td>true</td></tr><tr><td>Bit_64_Mode</td><td>true</td><td>true</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Packet_Overhead_Bytes</td><td>16  /* Added to A_Bytes per Packet */</td><td>16</td></tr></table> <h2>Hierarchical_Block</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>OUT3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Read_Latency</td><td>&quot;Read_Latency&quot;</td></tr><tr><td>Destination_Type</td><td>Global</td><td>Global</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>external1</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0</td><td>0</td></tr><tr><td>Value_1</td><td>5.0E-05</td><td>5.0E-5</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>DeviceInerface3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO_3&quot;</td><td>&quot;IO_3&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;DRAM_1&quot;</td><td>&quot;DRAM_1&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Write&quot;</td><td>&quot;Write&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;A_Bytes&quot;</td><td>&quot;A_Bytes&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;A_Priority&quot;</td><td>&quot;A_Priority&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>DeviceInerface2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO_2&quot;</td><td>&quot;IO_2&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;DRAM_2&quot;</td><td>&quot;DRAM_2&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Read&quot;</td><td>&quot;Read&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;A_Bytes&quot;</td><td>&quot;A_Bytes&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;A_Priority&quot;</td><td>&quot;A_Priority&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>AMBA_AHB2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_2&quot;</td><td>&quot;Bus_2&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td></tr><tr><td>Burst_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.005</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Round_Robin_Port_Array</td><td>{Bus_Name+&quot;_Port_1&quot;, Bus_Name+&quot;_Port_2&quot;, Bus_Name+&quot;_Port_3&quot;, Bus_Name+&quot;_Port_4&quot;, Bus_Name+&quot;_Port_5&quot;, Bus_Name+&quot;_Port_6&quot;, Bus_Name+&quot;_Port_7&quot;, Bus_Name+&quot;_Port_8&quot;}</td><td>{&quot;Bus_2_Port_1&quot;, &quot;Bus_2_Port_2&quot;, &quot;Bus_2_Port_3&quot;, &quot;Bus_2_Port_4&quot;, &quot;Bus_2_Port_5&quot;, &quot;Bus_2_Port_6&quot;, &quot;Bus_2_Port_7&quot;, &quot;Bus_2_Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM_2&quot;</td><td>&quot;DRAM_2&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>250.0</td><td>250.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 4.0, Prefetch 3.0, Write 4.0, ReadWrite 8.0, Erase 9.0&quot;</td><td>&quot;Read 4.0, Prefetch 3.0, Write 4.0, ReadWrite 8.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time * 1.0&quot;</td><td>&quot;Cycle_Time * 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr></table> <h2>Isolate_Input</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>OUT2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Read_Latency</td><td>&quot;Read_Latency&quot;</td></tr><tr><td>Destination_Type</td><td>Global</td><td>Global</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>OUT</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Write_Latency</td><td>&quot;Write_Latency&quot;</td></tr><tr><td>Destination_Type</td><td>Global</td><td>Global</td></tr></table> <h2>Util_Plot</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>min,mean,max</td><td>min,mean,max</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>false</td><td>false</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>Database</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address  A_Command\tA_Bytes\tA_Priority\tA_Destination    \\nMy_Task_1\t     LD_LDR\t  0\t    DRAM_2        32\t        1                Read         128\t2\t        DMA \\nMy_Task_2\t     LD_LDR\t  0\t    DRAM_1        32\t        1                Read         128       1\t        DMA \\nMy_Task_3\t     LD_LDR\t  0\t    DRAM_1        32\t        2                Read\t      128\t3\t        DMA \\n\\n</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address  A_Command\tA_Bytes\tA_Priority\tA_Destination    \\nMy_Task_1\t     LD_LDR\t  0\t    DRAM_2        32\t        1                Read         128\t2\t        DMA \\nMy_Task_2\t     LD_LDR\t  0\t    DRAM_1        32\t        1                Read         128       1\t        DMA \\nMy_Task_3\t     LD_LDR\t  0\t    DRAM_1        32\t        2                Read\t      128\t3\t        DMA \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>DMA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;DMA&quot;</td><td>&quot;DMA&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>32</td><td>&quot;32&quot;</td></tr><tr><td>Speed_Mhz</td><td>Bus_Speed_Mhz</td><td>&quot;Bus_Speed_Mhz&quot;</td></tr><tr><td>DMA_Channels</td><td>2</td><td>2</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr></table> <h2>TaskGenerator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Name</td><td>&quot;My_SoftGen&quot;</td><td>&quot;My_SoftGen&quot;</td></tr><tr><td>Mode_of_Operation</td><td>&quot;Loop&quot; /* Field gets input, Random selects a Task, Loop is sequential */</td><td>&quot;Loop&quot;</td></tr><tr><td>DEBUG</td><td>false /* To Debug Port */</td><td>false</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;TaskGenerator</td><td>ProcessorGenerator-&gt;TaskGenerator</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.005</td></tr><tr><td>Instruction_Mix_File</td><td>Instruction_Mix_Table.txt</td><td>&quot;Instruction_Mix_Table.txt&quot;</td></tr></table> <h2>ARM9_Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual.  \\n</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual.  \\n</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;ARM_INSTR&quot;</td><td>&quot;ARM_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n   Mnew Ra  Rb  Rc  Rd Re Rf  Rg Rh;   /* Label */\\n   ARM  EXEC             ; /* one execution unit */\\n   EXEC INT_1                ; /* ARM execution unit  */\\n\\nbegin INT_1                  ;\\n   MV_MOV 1 4                ; /* group MOVE */\\n   MV_MVN 1 4                ;\\n   MV_MRS 1 2                ;\\n   MV_MSR 3                  ;\\n\\n   ART_ADD 1 4               ; /* group ARITHMETIC */\\n   ART_ADC 1 4               ;\\n   ART_SUB 1 4               ;\\n   ART_SBC 1 3               ;\\n   ART_RSB 1 4               ;\\n   ART_RSC 1 4               ;\\n   ART_MUL 2 3               ;\\n   ART_MLA 2 3               ;\\n   ART_MULS 4                ;\\n   ART_MLAS 4                ;\\n   ART_UMULL 3 4             ;\\n   ART_UMLAL 3 4             ;\\n   ART_SMULL 3 4             ;\\n   ART_SMLAL 3 4             ;\\n   ART_UMULLS 5              ;\\n   ART_UMLALS 5              ;\\n   ART_SMULLS 5              ;\\n   ART_SMLALS 5              ;\\n   ART_CMP 1 4               ;\\n   ART_CMN 1 4               ;\\n   ART_QADD 1 2              ;\\n   ART_QSUB 1 2              ;\\n   ART_SMULXY 1              ;\\n   ART_SMULAXY 2             ;\\n   ART_SMULWX 1              ;\\n   ART_SMULAWX 2             ;\\n   ART_SMULALX 2 3           ;\\n   ART_CLZ 1                 ;\\n\\n   LGL_TST 1 4               ; /* group LOGICAL */\\n   LGL_TEQ 1 4               ;\\n   LGL_AND 1 4               ;\\n   LGL_EOR 1 4               ;\\n   LGL_ORR 1 4               ;\\n   LGL_BIC 1 4               ;\\n\\n   *BR_B 3                    ; /* group LOGICAL */\\n   BR_BL 3                   ; \\n   BR_BX 3                   ;\\n   BR_BLX 3                  ;\\n\\n   #LD_LDR 1 5               ; /* group LOAD */\\n   LD_LDRT 1 5               ; \\n   LD_LDRB 1 5               ; \\n   LD_LDRBT 1 5              ; \\n   LD_LDRSB 1 5              ; \\n   LD_LDRH 1 5               ; \\n   LD_LDRSH 1 5              ; \\n   LD_LDM_PC 5               ; \\n   LD_LDM 1 12               ; /* number of registers */\\n\\n   STR_STR 1                 ; /* group STORE */\\n   STR_STRT 1                ; \\n   STR_STRB 1                ; \\n   STR_STRBT 1               ; \\n   STR_STRH 1                ;\t\\n   STR_STM_PC 1 2            ;\\n   STR_STM 1 12              ; /* number of registers */\\n\\n   MISC_SWP 3                ; /* group MISCELLANEOUS */\\n   MISC_SWI 3                ; \\n   MISC_BKPT 3               ; \\n\\nend   INT_1                   ;</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n   Mnew Ra  Rb  Rc  Rd Re Rf  Rg Rh;   /* Label */\\n   ARM  EXEC             ; /* one execution unit */\\n   EXEC INT_1                ; /* ARM execution unit  */\\n\\nbegin INT_1                  ;\\n   MV_MOV 1 4                ; /* group MOVE */\\n   MV_MVN 1 4                ;\\n   MV_MRS 1 2                ;\\n   MV_MSR 3                  ;\\n\\n   ART_ADD 1 4               ; /* group ARITHMETIC */\\n   ART_ADC 1 4               ;\\n   ART_SUB 1 4               ;\\n   ART_SBC 1 3               ;\\n   ART_RSB 1 4               ;\\n   ART_RSC 1 4               ;\\n   ART_MUL 2 3               ;\\n   ART_MLA 2 3               ;\\n   ART_MULS 4                ;\\n   ART_MLAS 4                ;\\n   ART_UMULL 3 4             ;\\n   ART_UMLAL 3 4             ;\\n   ART_SMULL 3 4             ;\\n   ART_SMLAL 3 4             ;\\n   ART_UMULLS 5              ;\\n   ART_UMLALS 5              ;\\n   ART_SMULLS 5              ;\\n   ART_SMLALS 5              ;\\n   ART_CMP 1 4               ;\\n   ART_CMN 1 4               ;\\n   ART_QADD 1 2              ;\\n   ART_QSUB 1 2              ;\\n   ART_SMULXY 1              ;\\n   ART_SMULAXY 2             ;\\n   ART_SMULWX 1              ;\\n   ART_SMULAWX 2             ;\\n   ART_SMULALX 2 3           ;\\n   ART_CLZ 1                 ;\\n\\n   LGL_TST 1 4               ; /* group LOGICAL */\\n   LGL_TEQ 1 4               ;\\n   LGL_AND 1 4               ;\\n   LGL_EOR 1 4               ;\\n   LGL_ORR 1 4               ;\\n   LGL_BIC 1 4               ;\\n\\n   *BR_B 3                    ; /* group LOGICAL */\\n   BR_BL 3                   ; \\n   BR_BX 3                   ;\\n   BR_BLX 3                  ;\\n\\n   #LD_LDR 1 5               ; /* group LOAD */\\n   LD_LDRT 1 5               ; \\n   LD_LDRB 1 5               ; \\n   LD_LDRBT 1 5              ; \\n   LD_LDRSB 1 5              ; \\n   LD_LDRH 1 5               ; \\n   LD_LDRSH 1 5              ; \\n   LD_LDM_PC 5               ; \\n   LD_LDM 1 12               ; /* number of registers */\\n\\n   STR_STR 1                 ; /* group STORE */\\n   STR_STRT 1                ; \\n   STR_STRB 1                ; \\n   STR_STRBT 1               ; \\n   STR_STRH 1                ;\t\\n   STR_STM_PC 1 2            ;\\n   STR_STM 1 12              ; /* number of registers */\\n\\n   MISC_SWP 3                ; /* group MISCELLANEOUS */\\n   MISC_SWI 3                ; \\n   MISC_BKPT 3               ; \\n\\nend   INT_1                   ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>ARM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Mapping of ARM9 CPU architecture parameters to generic CPU\\nPlease NOTE that this is not goldenized and is only for Demo purpose.\\n</td><td>Mapping of ARM9 CPU architecture parameters to generic CPU\\nPlease NOTE that this is not goldenized and is only for Demo purpose.\\n</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;MAC_ARM9&quot;</td><td>&quot;MAC_ARM9&quot;</td></tr><tr><td>Processor_Setup</td><td>/* First row contains Column Names.                */\\nParameter_Name                   Parameter_Value   ;\\nProcessor_Instruction_Set:       ARM_INSTR\\nNumber_of_Registers:             16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz:             Processor_Speed\\nContext_Switch_Cycles:           200 /* switch between internal pipeline stages */\\nInstruction_Queue_Length:        3 /* This cab be assumed. Real ARM data ? */\\nNumber_of_Pipeline_Stages:       5 /* after 5\\'th stage is implemeted */\\nNumber_of_INT_Execution_Units:   1 /* 1 exection unit 1 coproc unit */\\nNumber_of_FP_Execution_Units:    0 /* no particular FP units */\\nMemory_Database_Reference:       DMADatabase\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1:            {Cache_Speed_Mhz=Processor_Speed, Size_KBytes=I_Cache_Size, Words_per_Cache_Line=8, Cache_Miss_Name=Cache}      \\nD_1:            {Cache_Speed_Mhz=Processor_Speed, Size_KBytes=D_Cache_Size, Words_per_Cache_Line=8, Cache_Miss_Name=Cache}      </td><td>/* First row contains Column Names.                */\\nParameter_Name                   Parameter_Value   ;\\nProcessor_Instruction_Set:       ARM_INSTR\\nNumber_of_Registers:             16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz:             Processor_Speed\\nContext_Switch_Cycles:           200 /* switch between internal pipeline stages */\\nInstruction_Queue_Length:        3 /* This cab be assumed. Real ARM data ? */\\nNumber_of_Pipeline_Stages:       5 /* after 5\\'th stage is implemeted */\\nNumber_of_INT_Execution_Units:   1 /* 1 exection unit 1 coproc unit */\\nNumber_of_FP_Execution_Units:    0 /* no particular FP units */\\nMemory_Database_Reference:       DMADatabase\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1:            {Cache_Speed_Mhz=Processor_Speed, Size_KBytes=I_Cache_Size, Words_per_Cache_Line=8, Cache_Miss_Name=Cache}      \\nD_1:            {Cache_Speed_Mhz=Processor_Speed, Size_KBytes=D_Cache_Size, Words_per_Cache_Line=8, Cache_Miss_Name=Cache}      </td></tr><tr><td>Pipeline_Stages</td><td>/* Pipeline stages in ARM  */\\nStage_Name   Execution_Location  Action  Condition ; \\n1_FETCH      I_1                 instr   none      ; /* Fetch */\\n2_DECODE     I_1                 wait    none      ; /* Decode */\\n3_EXECUTE    ARM                 exec    none      ; /* Execute ARM instr */\\n4_MEMORY     ARM                 wait    none      ; /* Wait for ARM instr */\\n4_MEMORY     D_1                 write   none      ; /* Write */\\n4_MEMORY     D_1                 read    none      ; /* Read */\\n5_WRITE_BACK D_1                 wait    none      ; /* Wait for Mem transaction */</td><td>/* Pipeline stages in ARM  */\\nStage_Name   Execution_Location  Action  Condition ; \\n1_FETCH      I_1                 instr   none      ; /* Fetch */\\n2_DECODE     I_1                 wait    none      ; /* Decode */\\n3_EXECUTE    ARM                 exec    none      ; /* Execute ARM instr */\\n4_MEMORY     ARM                 wait    none      ; /* Wait for ARM instr */\\n4_MEMORY     D_1                 write   none      ; /* Write */\\n4_MEMORY     D_1                 read    none      ; /* Read */\\n5_WRITE_BACK D_1                 wait    none      ; /* Wait for Mem transaction */</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Processor_Bits</td><td>32</td><td>32</td></tr><tr><td>Preemption_Enabled</td><td>true</td><td>true</td></tr></table> <h2>Power_Manager</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Manager_Name</td><td>&quot;Manager_1&quot;</td><td>&quot;Manager_1&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Manager_Setup</td><td>/* Power by Battery_Units, File (*.txt, *.csv, *.xml) or text below.              \\n                                                                                  \\n----------Name------------   ----------Power by State----------   --Transition--*/\\n    Architecture_Block       Standby  Active   Wait     Idle      Existing\tOnState\tOffState\tt_OnOff\tMhz\tVolts      ; \\nArchitecture_1_MAC_ARM9        75.0     200.0    100.0    100.0   Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_AHB_Bus         25.0     100.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_DRAM            50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_Cache           50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_DRAM_1          50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_DRAM_2          50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_DRAM_3          50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_PCIe_1          30.0     180.0   10.0     10.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_FPGA            40.0     200.0   10.0     10.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_FPGA1           40.0     200.0   10.0     10.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_FPGA2           40.0     200.0   10.0     10.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n   </td><td>/* Power by Battery_Units, File (*.txt, *.csv, *.xml) or text below.              \\n                                                                                  \\n----------Name------------   ----------Power by State----------   --Transition--*/\\n    Architecture_Block       Standby  Active   Wait     Idle      Existing\tOnState\tOffState\tt_OnOff\tMhz\tVolts      ; \\nArchitecture_1_MAC_ARM9        75.0     200.0    100.0    100.0   Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_AHB_Bus         25.0     100.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_DRAM            50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_Cache           50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_DRAM_1          50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_DRAM_2          50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_DRAM_3          50.0     150.0    0.0      0.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_PCIe_1          30.0     180.0   10.0     10.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_FPGA            40.0     200.0   10.0     10.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_FPGA1           40.0     200.0   10.0     10.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\nArchitecture_1_FPGA2           40.0     200.0   10.0     10.0     Standby\tActive\tStandby\t\t0.0\t100.0\t5.0        ; \\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n   </td></tr><tr><td>Async_State_Change</td><td>/* Async_State_Change.  First row contains Column Names, expressions valid for entries except Device Name. \\n                        where State to same State can extend a Power State                                 \\n--------Device Name-------  --Start------Expression------Next--- */\\nArchitecture_Block            State        Time          State   ; \\n</td><td>/* Async_State_Change.  First row contains Column Names, expressions valid for entries except Device Name. \\n                        where State to same State can extend a Power State                                 \\n--------Device Name-------  --Start------Expression------Next--- */\\nArchitecture_Block            State        Time          State   ; \\n</td></tr><tr><td>Expression_List</td><td>/* First row contains Column Names.                                \\n                                                                   \\n---------Reference--------  --------------Expression------------ */\\nName                                        Value                ; \\nCycle_t                     1.0E-6 / Mhz                         ; \\n</td><td>/* First row contains Column Names.                                \\n                                                                   \\n---------Reference--------  --------------Expression------------ */\\nName                                        Value                ; \\nCycle_t                     1.0E-6 / Mhz                         ; \\n</td></tr><tr><td>Battery_Units</td><td>Milli_Watts</td><td>Milli_Watts</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr></table> <h2>Ave_Pwr</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>Instant</td><td>Instant</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>DRAM2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed_Mhz</td><td>400.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 4.0, Prefetch 6.0, Write 4.0, ReadWrite 4.0, Erase 9.0&quot;</td><td>&quot;Read 4.0, Prefetch 6.0, Write 4.0, ReadWrite 4.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>2</td><td>2</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr></table> <h2>Cache</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache&quot;</td><td>&quot;Cache&quot;</td></tr><tr><td>Miss_Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Cache_Speed_Mhz</td><td>Bus_Speed_Mhz</td><td>400.0</td></tr><tr><td>Cache_Size_KBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Words_per_Cache_Line</td><td>16</td><td>16</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Cache_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:100,200 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:100,200 */&quot;</td></tr><tr><td>Cache_Hit_Expression</td><td>&quot;rand(0.0,1.0) &lt;= 1.0&quot;</td><td>&quot;rand(0.0,1.0) &lt;= 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>DRAM1</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM_1&quot;</td><td>&quot;DRAM_1&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>250.0</td><td>250.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 4.0, Prefetch 6.0, Write 4.0, ReadWrite 8.0, Erase 9.0&quot;</td><td>&quot;Read 4.0, Prefetch 6.0, Write 4.0, ReadWrite 8.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time * 1.0&quot;</td><td>&quot;Cycle_Time * 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr></table> <h2>Bridge</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge&quot;</td><td>&quot;Bridge&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.005</td></tr></table> <h2>AMBA_AHB</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>Processor_Speed</td><td>100.0</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td></tr><tr><td>Burst_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>0.005</td></tr><tr><td>FIFO_Buffers</td><td>1024</td><td>1024</td></tr><tr><td>Round_Robin_Port_Array</td><td>{Bus_Name+&quot;_Port_1&quot;, Bus_Name+&quot;_Port_2&quot;, Bus_Name+&quot;_Port_3&quot;, Bus_Name+&quot;_Port_4&quot;, Bus_Name+&quot;_Port_5&quot;, Bus_Name+&quot;_Port_6&quot;, Bus_Name+&quot;_Port_7&quot;, Bus_Name+&quot;_Port_8&quot;}</td><td>{&quot;Bus_1_Port_1&quot;, &quot;Bus_1_Port_2&quot;, &quot;Bus_1_Port_3&quot;, &quot;Bus_1_Port_4&quot;, &quot;Bus_1_Port_5&quot;, &quot;Bus_1_Port_6&quot;, &quot;Bus_1_Port_7&quot;, &quot;Bus_1_Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr></table> <h2>FPGA_Src</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>6.0e-9</td><td>6.0E-9</td></tr><tr><td>Value_1</td><td>5.0E-05</td><td>5.0E-5</td></tr><tr><td>Value_2</td><td>5.0E-05</td><td>5.0E-5</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>DeviceInerface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO_1&quot;</td><td>&quot;IO_1&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;DRAM_2&quot;</td><td>&quot;DRAM_2&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Read&quot;</td><td>&quot;Read&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;A_Bytes&quot;</td><td>&quot;A_Bytes&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;A_Priority&quot;</td><td>&quot;A_Priority&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table>

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