RedundantProgrammableArrayController_HW_V3
Browsable image of the model.
- For an executable version,
- Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
- To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.
The need to improve productivity and maintain an edge with customer’s demand for innovation, industrial markets has adopted technology in their production activity. Managing workload, performance and optimize the system is very important to deliver quality products on time-to-market. VisualSim enables designer and architects to evaluate the workload, power consumption and optimize the system accordingly and supports to develop a highly sustainable product with greater flexibility for future enhancements.
The growth of technology developments in processors, data storage, and chip design, etc., opened door to endless opportunities in the computing industry. With opportunities, the need to collaborate and communicate with vendors, clients, architects and development team has increased. Time-to-market and power bandwidth determine the sustainability of product in the global market. Early exploration analysis and power analysis would enhance architects and designers to develop innovative products and create new revenue opportunities.
Model Overview
In this model, we have considered distributed IO
architecture. This includes single M580 Processor Rack with a Dual Core ARM
Processor. We have also considered two STB I/O modules with multiple sensors
connected to it, two distributed devices that are connected to ConneXium
Management Switch. The two devices connected to ConneXium Management switch are
for Energy Supervision and altivar Process variable speed drive.
One of the Processor modules in PAC acts as the primary,
which runs the application by executing program logic and operating RIO drops
and distributed equipment; the other PAC acts as the standby PAC. The primary
PAC updates the standby PAC at the beginning of each scan. The standby is ready
to assume control within one scan if the primary stops communications.
Primary and standby states are interchangeable. When the PACs are running, either PAC can enter the primary state. When one running PAC becomes primary, the other running PAC may be in the standby or wait state. Explorations are focused around latency between nodes, end-to-end latency, and application performance on the target platform, pipeline utilization, processor stalls and network latency.
Block Diagram
Fig 1. Block Diagram Of the Programmable Automation Control
The model captures the following
- MIPS of CPU_1 and CPU_2
- Latency at ModiconSTB1
- Latency at ModiconSTB2
- Latency at Altivar
- Latency at EnergySupervision
 Fig. 1 CPU_1 MIPS Plot |  Fig. 2 CPU_2 MIPS Plot |
 Fig. 3 Latency at ModiconSTB1Plot |  Fig. 4 Latency at ModiconSTB1Plot |
 Fig. 5 Latency at Altivar |  Fig. 6 Latency at EnergySupervision |