Evaluate_Bus_Model_Step_4
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"This Model illustrates a simple bus model that evaluates bus performance in terms of latency, throughput, and utilization relative to burst size. Each Bus Port makes requests to a common Bus Arbiter, and then delays transactions based on the size of transactions.
What is the best burst size for a Bus running at 100 Mhz, 4 Byte width, in terms of Latency and Throughput? Assume the following:
-- Separate Address cycle for each Xfer.
-- Data Sizes of 16, 32, or 64 Bytes (Uniform Random).
-- Burst Size of 24 or 48 Bytes (Model Parameter).
-- Option to set Priority, all same in this model.
-- Order of Arrival (FCFS) determines processing.
Tradeoff Conclusion:
The plot compares the Figure of Merit, Throughput divided by Latency, so the highest value shows the best performance by Data Size. Here the 16 Byte transfer excels, however, it always arrives first (see detailed bus port, arbiter order), so has a processing preference, read better latency relative to other ports.
Tradeoff Conclusion:
This shows the Figure of Merit, Throughput divided by Latency, so the highest value shows the best performance by Data Size. Now the 32 Byte or 64 Byte excels, based on having a higher priority for Port_2 relative to other bus ports".