Modeling SPI3 using VisualSim

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Model of the PHY-Link Layer Interface part of the SPI3 Protocol Standard

This model has been created based on the specification laid out by the Optical Internetworking Forum (OIF) titled: OIF-SPI3-01.0 from June 2000. The title of the committee is the Physical-Link Layer Interface and the Titel of this paper is: System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices.

SPI-3 fulfills the need for system designers to target a standard POS Physical Layer interface. Although targeted at implementing POS, the SPI-3 specification is not restricted to this application. It provides a versatile bus interface for exchanging packets within a communication system. SPI-3 defines the requirements for interoperable single-PHY (one PHY layer device connected to one Link Layer device) and multi-PHY (multiple PHY layer devices connected to one Link Layer device) applications. It stresses simplicity of operation to allow forward migration to more elaborate PHY and Link Layer devices.

The model has been constructed as a single PHY to single Link-Layer connection. it can be easily extended by using the Virtual Connectors and adding additional segmenting setup to create a multi-multi scenario. This model contains the

Fragment and reassembly
The signaling protocol used to communicate data
The data structure used to store the data into holding FIFO’s
Queuing setup for the PHY and Link Layers
Models the one way messaging from the Link Layer to the PHY. The reverse could be created by copying the existing blocks and reversing the flow of data.

This model supports a 32-bit bus structure. The bus interface is point-to-point (one output driving only one input load) and thus a 32-bit data bus would support only one device. This SPI-3 model defaults to a transfer clock rate of 104 MHz. The clock rate has been made a parameter and different clock rates can be setup simply by modifying the Clock Rate parameter. Generally, devices targeted at single or multi-PHY applications, where the aggregate PHY bit rate approaches 622 Mbit/s will use the 8-bit data bus structure with a 104 MHz FIFO clock rate. Devices targeted at applications where the aggregate PHY bit rate approaches 2.4 Gbit/s will use the 32-bit data bus structure with a 104 MHz FIFO clock rate.

The SPI-3 model packet interface supports transmit and receive data transfers at clock rates independent of the line bit rate. The line rates are defined by the rate of packet creation at the Data Structure Generator blocks. The PHY layer devices support packet rate decoupling using FIFO Queues. All of the Control signals required to conduct the transfer between the two layers have been modeled either in the Data Structure that is transfered or at the top-level of the model using memory variables. The data structure also includes the actual transmitted for further algorithm processing at the PHY for error corrections, processor for searches, TCP termination and security tasks.

Below is the Data Structure that is transmitted through the model:
_______________________________________________________________________________________
Packet_Type            String Transmit                              ;
Packet_Bytes_Left      int     20                                    ;
Packet_Delay           double 0.0                                   ;
Enable                 boolean true                                  ;
Data                   binary 32'b11010101010101010101010101010101 ;
Data_Int               int     32                                    ;
Modulo                 binary 2'00                                  ;
Modulo_Int             int      0                                    ;
Valid                  boolean true                                  ;
Start_Packet           boolean true                                  ;
End_Packet             boolean false                                 ;
Error_Packet           boolean false                                 ;
Start_Xmit             int     64                                    ;
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Notes on the Model:

Modify the parameters in the model canvas and view the results being updated.
View Saw-Tooth packet latency graph that validates the accuracy of the model
The parameter Bus_Cycle_Time contains the 104 which indicates the 104 MHz. Modify this value to create other data rates.
View the new While blocks as it creates the fragments based on a decision and has a delay between fragment creation to accound for hardware overhead.
The entire interface was created with 10 different blocks instantiated 25 in all.

Model and Simulation Plots:

Results:
The three graphs pages describe the following:

Packet Latency: The plot computes the latency between the arrival at the Link Layer FIFO until it leaves the PHY FIFO. As expected this is a saw-tooth.
Statistics from PHY and Link-Layer: The statistics show the buffering and utilization of the FIFOs at the PHY and the Link Layer. In addition, view the transmitted Data Structure at the PHY and the Link Layer.