OVS_Switch_Model_V6

Early analysis of OVS Switch based System for Optimal Performance and Power Requirements

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Please click on green button in the toolbar or press CTRL+R to start simulation. User can modify the model parameters by double clicking on the parameters and block parameters by double clicking on the library blocks.

Introduction

Open vSwitch, sometimes abbreviated to OVS, is a production-quality open-source implementation of a distributed virtual multilayer switch. The main purpose of Open vSwitch is to provide a switching stack for hardware virtualization environments, while supporting multiple protocols and standards used in computer networks.

Open vSwitch is a software implementation of a virtual multilayer network switch, designed to enable effective network automation through programmatic extensions, while supporting standard management interfaces and protocols such as NetFlow, sFlow, SPAN, RSPAN, CLI, LACP and 802.1ag. In addition, Open vSwitch is designed to support transparent distribution across multiple physical servers by enabling creation of cross-server switches in a way that abstracts out the underlying server architecture. OVS is also used on some dedicated switching hardware and it can be a critical part of the Software Defined Networking. In this document we will be showing you how a OVS based Network architecture can be setup and conduct verities of trade-off analysis studies to meet performance and power requirements even before the implementation details are available. The sample block diagram of the proposed system architecture is shown in figure 1.0 below.

Figure 1.0: OVS based System Block Diagram

We at Mirabilis Design developed an even based simulation model using VisualSim using configurable prebuilt graphical library blocks. The Simulation model of the proposed system architecture is shown in figure 2.0

Figure 2: VisualSim Model

The major purpose of developing statistical level simulation model at the very early stages of product development is to gain more confidence over the selected architecture configurations. Availability of simulation models even before the availability of implementation details and IP’s will enable the designers to select the optimal system configuration that meets user requirements and also make sure that the resources are utilized optimally. Statistical level simulation model can be constructed with very minimal information but it can be extended with details at the later stages for more accuracy. In this model we have considered many assumptions which include clock speed of OVS Switch, PCIe clock speed, Ethernet speed, and abstract details on the functionality of LB Block, DPI, FW, SSL, IPSec and Compression/Decompression block.

We have constructed the complete simulation model in eight man hours and spent fairly good amount of time on conducting analysis. During analysis we focused on end-to-end latency from Host Computer to Ethernet MAC and Ethernet MAC to Host Computer, average power consumption of complete system, utilization of resources and timing diagram to understand resource activity.

Analysis and Reports

As part of the analysis we have parameterized number of values and these includes Traffic rate of Host Computer, Traffic Rate of Ethernet, Clock speed of DMA, DDR, OVS Switch, PCIe, Packet Parser. We ran the simulation on a 2.6 GHz Microsoft Windows 8.1 platform with 4 GB RAM. We simulated the model for 500 ms real time and the VisualSim took 121.610 seconds. Analysis was conducted by varying the model parameters as mentioned above and looked at the latency and utilization of resources.

Analysis 1:

Change the parameters mentioned below and run simulation.

Module – PCIe/DMA

Parameters

Inter_Arrival_Time = 1.0e-4

DMA_Speed = 500.0e6

PCIe_Speed = 500.0e6

DDR_Speed = 500.0e6

Module – OVS Switch

Parameters

Switch Speed = 500.0e6

Module Ethernet_MAC

Parameters

Inter_Arrival_Time = 1.0e-2

Module – Packet Parser

Parameters

Clock_Speed = 500.0e6

The Simulation Results are shown below

Figure 3.0: End-to-End Latency – From Host Computer to Ethernet MAC

Figure 4.0: End-to-End Latency – From Ethernet MAC to Host Computer

Figure 5.0: Average Power Consumption of Complete System (Red)

Analysis 2:

Change the parameters mentioned below and run simulation.

Module – PCIe/DMA

Parameters

Inter_Arrival_Time = 1.0e-4

DMA_Speed = 500.0e6

PCIe_Speed = 500.0e6

DDR_Speed = 500.0e6

Module – OVS Switch

Parameters

Switch Speed = 1000.0e6

Module Ethernet_MAC

Parameters

Inter_Arrival_Time = 1.0e-4

Module – Packet Parser

Parameters

Clock_Speed = 500.0e6

The Simulation Results are shown below

Figure 6.0: End-to-End Latency – From Host Computer to Ethernet MAC

Figure 7.0: End-to-End Latency – From Ethernet MAC to Host Computer

Figure 8.0: Average Power consumption of Complete System (Red)