Satellite Modem

Defense and Space

  • Radar System
    Hardware-software mapping of a Radar system for a aircraft.
  • Software-Defined Radio
    Software Defined Radio with ADI9361 and ADI9371
  • Air-Ground Mission
     Network of satellites, aircrafts and ground stations
  • Satellite Modem
  • UAV
    Hardware architetcures
  • Jet Engine Controller
    Designing the controller
  • Satellite Systems
    Acquisition, Processing, Storage and Communication with Power and animation
  • Cubesat
    Implementation of a Air Force Cubesat model that can be used as a template to create any Cubesat architecture. Include support for battery, different activities per orbit and response times.

Satellite_Modem_V1

Browsable image of the model.

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    Windows- Compatibility:Windows 10 or higher (*)
    macOS - Compatibility:macOS 10.15 (Catalina) or higher (*)
    Linux - Compatibility:Ubuntu 18.04 LTS or higher (*)
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  • To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.
Satellite_Modem_V1model <h2>TMS320DM2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>Bus_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr></table> <h2>TMS320DM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>NAND_Flash_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr></table> <h2>Hierarchical_Block</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>Comm_Delay</td><td>60.0e-3</td><td>0.06</td></tr></table> <h2>ADC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>DAC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Ethernet Interface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>IP_Data_Rate</td><td>1280.0 /* 100 Mbps */</td><td>1280.0</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>0</td><td>0</td></tr></table> <h2>TMS320DM6446</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>Processor_Speed</td><td>400.0 /* MHz */</td><td>400.0</td></tr><tr><td>Bus_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr><tr><td>NAND_Flash_Speed</td><td>200.0 /* MHz */</td><td>200.0</td></tr></table> <h2>M&C and Waveform Selection</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>FPGA_Clock_Speed</td><td>125.0 /* MHz */</td><td>125.0</td></tr></table> <h2>DeModulator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>FEC Decoder</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Alignment_Dly</td><td>6 /*cycles */</td><td>6</td></tr><tr><td>Transcoding_Mapping_Dly</td><td>2 /*clock cycles*/</td><td>2</td></tr><tr><td>Parity_Generation</td><td>2 /*Cycles*/</td><td>2</td></tr></table> <h2>Differential Decoder</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>DE_Delay</td><td>2</td><td>2</td></tr></table> <h2>Descrambler</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Dly_Cycles</td><td>10</td><td>10</td></tr></table> <h2>Data De-Framer</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Modulator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Modulation mapping based on Symbol (BPSK, 4-PSK, 8-PSK, 16-QAM, 64-QAM, 128-QAM))</td><td>Modulation mapping based on Symbol (BPSK, 4-PSK, 8-PSK, 16-QAM, 64-QAM, 128-QAM))</td></tr><tr><td>Modulation_Factor</td><td>&quot;8PSK&quot; /* &quot;QPSK&quot;, &quot;8PSK&quot;, &quot;16QAM&quot;, &quot;64QAM&quot;*/</td><td>&quot;8PSK&quot;</td></tr></table> <h2>FEC Encoder</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Should perform based on INTELSAT FEC rates</td><td>Should perform based on INTELSAT FEC rates</td></tr><tr><td>Alignment_Dly</td><td>6 /*cycles */</td><td>6</td></tr><tr><td>Transcoding_Mapping_Dly</td><td>2 /*clock cycles*/</td><td>2</td></tr><tr><td>Parity_Generation</td><td>2 /*Cycles*/</td><td>2</td></tr></table> <h2>Differential Encoder</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>I bit delay and XOR Operation</td><td>I bit delay and XOR Operation</td></tr><tr><td>DE_Delay</td><td>2</td><td>2</td></tr></table> <h2>Scrambler</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Scrambler will randomize the data stream that needs to be transmitted.</td><td>Scrambler will randomize the data stream that needs to be transmitted.</td></tr><tr><td>Dly_Cycles</td><td>10</td><td>10</td></tr></table> <h2>Data Framer</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Data Framer Receives IP data through Ethernet Interface. \\nIn this model the size of data received is 100 Mb. DataFramer \\nwill fragment the data into 25 bits (Need to check). Full Frame will\\nwill be sent out for every 125 useconds total of 12500 bits\\n </td><td>Data Framer Receives IP data through Ethernet Interface. \\nIn this model the size of data received is 100 Mb. DataFramer \\nwill fragment the data into 25 bits (Need to check). Full Frame will\\nwill be sent out for every 125 useconds total of 12500 bits\\n </td></tr><tr><td>Overhead_Rate</td><td>125.0e-6</td><td>1.25E-4</td></tr></table>

This model of a Satellite modem uses a Kintex 7 FPGA form Xilinx