RISC-V Processor System

This model shows VisualSim's RISC-V implementation by simulating a network application task profile provided by
NpBench. As soon as the model opens click on the RUN button (Green) in the toolbar at the top. You will see a bunch
of windows opening. These windows show the results obtained from the simulation such as Task Latency, Task Set
Latency, Power Consumption, and Statistics of the components of the model.

For further exploration of the model:
1) Double-Click on any block to get the specifications and parameters used for the block.
2)Some blocks, called hierarchical blocks, contain components within them. To see the working of a hierarchical block,
Right-Click on the block and select "Open Block". The hierarchical blocks present in this model are "Task Generator" and "Plots"

---------------------------------------RISC-V Model Description---------------------------------------

The Task Generator Hierarchical Block contains a traffic block, expression lists and a queue to simulate a set of 10 tasks in order.
The task profile is based on NpBench: A Network Processor benchmark tool. Each Task contains a random selection of instructions
based on the percentage of the kind of instruction defined in the task profile. The task generator links to an instuction mix table
which contains all details relating to the input tasks.

The simulated tasks are given to the Processor Block. Here, all the instructions are executed according to the details filled in the
"RISC-V ISA" Block and the pipeline specified within the Processor block. All the executed instructions come out of the processor
through the output port of the block and the data structures from this port are used for plotting results.

The Processor is also connected to an external Cache and DRAM via a bus. These are memory blocks were the processor gets
data from when a miss occurs within internal cache. It also has DMA connected, which will give the processor the power to access
the DRAM directly.

Click here to view the ppt