Network_Processor

Browsable image of the model.

Network_Processormodel <h2>ExpressionList4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Destination = &quot;PPC_7410_1&quot;\\ninput.A_Hop = input.A_Destination\\n</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Destination = &quot;PPC_7410_1&quot;\\ninput.A_Hop = input.A_Destination\\n</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>ExpressionList3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template for List of Expressions. \\n Result_A = MyRegExpression_A_or_None \\n Result_B = MyRegExpression_B_or_None \\n Result_C = MyRegExpression_C_or_None \\n Result_D = MyRegExpression_D_or_None \\n End of Expressions */ \\n</td><td>/* Template for List of Expressions. \\n Result_A = MyRegExpression_A_or_None \\n Result_B = MyRegExpression_B_or_None \\n Result_C = MyRegExpression_C_or_None \\n Result_D = MyRegExpression_D_or_None \\n End of Expressions */ \\n</td></tr><tr><td>Output_Ports</td><td>output,out</td><td>&quot;output,out&quot;</td></tr><tr><td>Output_Values</td><td>input,input</td><td>&quot;input,input&quot;</td></tr><tr><td>Output_Conditions</td><td>(input.A_Destination != &quot;Architecture_1&quot;), !(input.A_Destination != &quot;Architecture_1&quot;)</td><td>&quot;(input.A_Destination != &quot;Architecture_1&quot;), !(input.A_Destination != &quot;Architecture_1&quot;)&quot;</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Task_Name = &quot;Load_Data&quot;\\ninput.A_Instruction = {&quot;LDR&quot;}\\n</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Task_Name = &quot;Load_Data&quot;\\ninput.A_Instruction = {&quot;LDR&quot;}\\n</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Task_Name = &quot;Store_Data&quot;\\ninput.A_Instruction = {&quot;STR&quot;}\\ninput.A_Source = &quot;PPC_7410_1&quot;\\n</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Task_Name = &quot;Store_Data&quot;\\ninput.A_Instruction = {&quot;STR&quot;}\\ninput.A_Source = &quot;PPC_7410_1&quot;\\n</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>TriggeredTraffic2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr></table> <h2>Fork</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>TriggeredTraffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>PCIe_Bus</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;PCIe_2&quot;</td><td>&quot;PCIe_2&quot;</td></tr><tr><td>Number_of_Lanes</td><td>16 /* Can be an array */</td><td>16</td></tr><tr><td>Slave_Buffer</td><td>512 /* Max Bytes @ Slave */</td><td>512</td></tr><tr><td>Master_Buffer</td><td>512 /* Max Bytes @ Master */</td><td>512</td></tr><tr><td>Sim_Time</td><td>1.0E-3</td><td>1.0E-3</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td></tr><tr><td>Header_Bytes</td><td>16 /* 32 Bit Mode, includes CRC Bytes */</td><td>16</td></tr><tr><td>Number_of_Ports</td><td>{12, 12} /* Master, Endpoint Ports */</td><td>{12, 12}</td></tr><tr><td>BER</td><td>1.0E-11</td><td>1.0E-11</td></tr><tr><td>Max_Payload_Size</td><td>64 /* Write, Read Data */</td><td>64</td></tr><tr><td>Max_Payload_Req_Size</td><td>128 /* Read Requests */</td><td>128</td></tr><tr><td>PCIe_Gen_1</td><td>250.0 /* DO NOT MODIFY */</td><td>250.0</td></tr><tr><td>PCIe_Gen_2</td><td>500.0 /* DO NOT MODIFY */</td><td>500.0</td></tr><tr><td>PCIe_Gen_3</td><td>985.6 /* DO NOT MODIFY */</td><td>985.6</td></tr><tr><td>PCIe_Gen_4</td><td>1969.2 /* DO NOT MODIFY */</td><td>1969.2</td></tr><tr><td>PCIe_MBps</td><td>PCIe_Gen_2 /* Per Lane */</td><td>500.0</td></tr><tr><td>Read_to_Write_Ratio</td><td>0.5 /* 0.0 to 1.0 */</td><td>0.5</td></tr><tr><td>Devices_Attached_to_Slaves</td><td>{{&quot;DDR3&quot;},{&quot;DRAM_2&quot;},{&quot;DRAM_3&quot;},{&quot;Dev_4&quot;},{&quot;Dev_5&quot;},{&quot;Dev_6&quot;},{&quot;Dev_7&quot;},{&quot;Dev_8&quot;},{&quot;Dev_9&quot;},{&quot;Dev_10&quot;},{&quot;Dev_11&quot;},{&quot;Dev_12&quot;}}</td><td>{{&quot;DDR3&quot;}, {&quot;DRAM_2&quot;}, {&quot;DRAM_3&quot;}, {&quot;Dev_4&quot;}, {&quot;Dev_5&quot;}, {&quot;Dev_6&quot;}, {&quot;Dev_7&quot;}, {&quot;Dev_8&quot;}, {&quot;Dev_9&quot;}, {&quot;Dev_10&quot;}, {&quot;Dev_11&quot;}, {&quot;Dev_12&quot;}}</td></tr><tr><td>Root_Complex_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Endpoint_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Enable_Plots</td><td>true</td><td>true</td></tr><tr><td>Bit_64_Mode</td><td>true</td><td>true</td></tr><tr><td>Device_Attached_to_Slave_port</td><td>{&quot;&quot;}</td><td>{&quot;&quot;}</td></tr><tr><td>Device_Attached_to_Slave_port2</td><td>{&quot;&quot;}</td><td>{&quot;&quot;}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr></table> <h2>PCIe_Bus3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;PCIe_1&quot;</td><td>&quot;PCIe_1&quot;</td></tr><tr><td>Number_of_Lanes</td><td>16 /* Can be an array */</td><td>16</td></tr><tr><td>Slave_Buffer</td><td>512 /* Max Bytes @ Slave */</td><td>512</td></tr><tr><td>Master_Buffer</td><td>512 /* Max Bytes @ Master */</td><td>512</td></tr><tr><td>Sim_Time</td><td>1.0E-3</td><td>1.0E-3</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td></tr><tr><td>Header_Bytes</td><td>16 /* 32 Bit Mode, includes CRC Bytes */</td><td>16</td></tr><tr><td>Number_of_Ports</td><td>{12, 12} /* Master, Endpoint Ports */</td><td>{12, 12}</td></tr><tr><td>BER</td><td>1.0E-11</td><td>1.0E-11</td></tr><tr><td>Max_Payload_Size</td><td>64 /* Write, Read Data */</td><td>64</td></tr><tr><td>Max_Payload_Req_Size</td><td>128 /* Read Requests */</td><td>128</td></tr><tr><td>PCIe_Gen_1</td><td>250.0 /* DO NOT MODIFY */</td><td>250.0</td></tr><tr><td>PCIe_Gen_2</td><td>500.0 /* DO NOT MODIFY */</td><td>500.0</td></tr><tr><td>PCIe_Gen_3</td><td>985.6 /* DO NOT MODIFY */</td><td>985.6</td></tr><tr><td>PCIe_Gen_4</td><td>1969.2 /* DO NOT MODIFY */</td><td>1969.2</td></tr><tr><td>PCIe_MBps</td><td>PCIe_Gen_2 /* Per Lane */</td><td>500.0</td></tr><tr><td>Read_to_Write_Ratio</td><td>0.5 /* 0.0 to 1.0 */</td><td>0.5</td></tr><tr><td>Devices_Attached_to_Slaves</td><td>{{&quot;DDR3&quot;},{&quot;DRAM_2&quot;},{&quot;DRAM_3&quot;},{&quot;Dev_4&quot;},{&quot;Dev_5&quot;},{&quot;Dev_6&quot;},{&quot;Dev_7&quot;},{&quot;Dev_8&quot;},{&quot;Dev_9&quot;},{&quot;Dev_10&quot;},{&quot;Dev_11&quot;},{&quot;Dev_12&quot;}}</td><td>{{&quot;DDR3&quot;}, {&quot;DRAM_2&quot;}, {&quot;DRAM_3&quot;}, {&quot;Dev_4&quot;}, {&quot;Dev_5&quot;}, {&quot;Dev_6&quot;}, {&quot;Dev_7&quot;}, {&quot;Dev_8&quot;}, {&quot;Dev_9&quot;}, {&quot;Dev_10&quot;}, {&quot;Dev_11&quot;}, {&quot;Dev_12&quot;}}</td></tr><tr><td>Root_Complex_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Endpoint_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Enable_Plots</td><td>true</td><td>true</td></tr><tr><td>Bit_64_Mode</td><td>true</td><td>true</td></tr><tr><td>Device_Attached_to_Slave_port</td><td>{&quot;&quot;}</td><td>{&quot;&quot;}</td></tr><tr><td>Device_Attached_to_Slave_port2</td><td>{&quot;&quot;}</td><td>{&quot;&quot;}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr></table> <h2>Instruction_Set2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;Altivec&quot;</td><td>&quot;Altivec&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set or File Path. */\\n Mnew Rx Ry Rz ; /* Label */\\n VPU FP_1 ;\\n\\nbegin FP_1 ; /* Group */\\n vpu_sim_int 1 ;\\n vpu_com_int 3 ;\\n vpu_fp 4 ;\\nend FP_1 ;</td><td>/* Instruction Set or File Path. */\\n Mnew Rx Ry Rz ; /* Label */\\n VPU FP_1 ;\\n\\nbegin FP_1 ; /* Group */\\n vpu_sim_int 1 ;\\n vpu_com_int 3 ;\\n vpu_fp 4 ;\\nend FP_1 ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>Host</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Rate_in_Cycles</td><td>256.0</td><td>256.0</td></tr><tr><td>Bus_Command</td><td>&quot;Read&quot;</td><td>&quot;Read&quot;</td></tr><tr><td>Bus_Transaction_Size_Bytes</td><td>32</td><td>32</td></tr><tr><td>Master_Source</td><td>&quot;uProcessor2&quot;</td><td>&quot;uProcessor2&quot;</td></tr><tr><td>Master_Destination</td><td>&quot;DDR3&quot;</td><td>&quot;DDR3&quot;</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr></table> <h2>OUT</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Ether_DMA</td><td>&quot;Ether_DMA&quot;</td></tr><tr><td>Destination_Type</td><td>Global</td><td>Global</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Switched_Ethernet</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>EtherSwitch_Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>EtherSwitch_Bytes_per_Frame</td><td>1500</td><td>1500</td></tr><tr><td>EtherSwitch_Overhead_Bytes_per_Frame</td><td>20</td><td>20</td></tr><tr><td>EtherSwitch_Full_Duplex</td><td>true</td><td>true</td></tr></table> <h2>Host1</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Rate_in_Cycles</td><td>256.0</td><td>256.0</td></tr><tr><td>Bus_Command</td><td>&quot;Read&quot;</td><td>&quot;Read&quot;</td></tr><tr><td>Bus_Transaction_Size_Bytes</td><td>32</td><td>32</td></tr><tr><td>Master_Source</td><td>&quot;uProcessor&quot;</td><td>&quot;uProcessor&quot;</td></tr><tr><td>Master_Destination</td><td>&quot;DDR3&quot;</td><td>&quot;DDR3&quot;</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr></table> <h2>Join</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>ExpressionList5</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Task_Name = (input.A_Task_Name == &quot;Store_Data&quot;)?&quot;Start_PPC&quot;:&quot;Done&quot;\\ninput.A_Destination = (input.A_Task_Name==&quot;Store_Data&quot;)?&quot;PPC_7410_1&quot;:input.A_Destination\\ninput.A_Hop = input.A_Destination</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Task_Name = (input.A_Task_Name == &quot;Store_Data&quot;)?&quot;Start_PPC&quot;:&quot;Done&quot;\\ninput.A_Destination = (input.A_Task_Name==&quot;Store_Data&quot;)?&quot;PPC_7410_1&quot;:input.A_Destination\\ninput.A_Hop = input.A_Destination</td></tr><tr><td>Output_Ports</td><td>output,output2</td><td>&quot;output,output2&quot;</td></tr><tr><td>Output_Values</td><td>input,input</td><td>&quot;input,input&quot;</td></tr><tr><td>Output_Conditions</td><td>(input.A_Task_Name==&quot;Start_PPC&quot;),(input.A_Task_Name==&quot;Start_PPC&quot;)</td><td>&quot;(input.A_Task_Name==&quot;Start_PPC&quot;),(input.A_Task_Name==&quot;Start_PPC&quot;)&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>IN</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>Start_Process</td><td>&quot;Start_Process&quot;</td></tr><tr><td>Destination_Type</td><td>Global</td><td>Global</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ; \\nDMA PPC_7410_1 DMA Dout ; /* Device to device like DMA */</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ; \\nDMA PPC_7410_1 DMA Dout ; /* Device to device like DMA */</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Pipeline</td><td>Pipeline</td></tr></table> <h2>DMA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Timing_Diagram</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Proc_Name</td><td>&quot;PPC_7410_1&quot;</td><td>&quot;PPC_7410_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;PPC_7410_1&quot; + &quot;_Bus&quot;</td><td>&quot;PPC_7410_1_Bus&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_1&quot;</td><td>&quot;Cache_1&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;DDR3&quot;</td><td>&quot;DDR3&quot;</td></tr><tr><td>AXI_Name</td><td>&quot;AXI_Top&quot;</td><td>&quot;AXI_Top&quot;</td></tr><tr><td>Memory_Controller_Name</td><td>&quot;DDR&quot;</td><td>&quot;DDR&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;DDR3&quot;</td><td>&quot;DDR3&quot;</td></tr><tr><td>_explanation</td><td>Hardware Setup-&gt;Timing_Diagram</td><td>Hardware Setup-&gt;Timing_Diagram</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr></table> <h2>Sink</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>TaskGenerator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Name</td><td>&quot;Software_Generator&quot;</td><td>&quot;Software_Generator&quot;</td></tr><tr><td>Mode_of_Operation</td><td>&quot;Random&quot; /* Field gets input, Random selects a Task, Loop is sequential */</td><td>&quot;Random&quot;</td></tr><tr><td>DEBUG</td><td>false /* To Debug Port */</td><td>false</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;TaskGenerator</td><td>ProcessorGenerator-&gt;TaskGenerator</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>3.0E-4</td></tr><tr><td>Instruction_Mix_File</td><td>Instruction_Mix_Table_Test.txt</td><td>&quot;Instruction_Mix_Table_Test.txt&quot;</td></tr></table> <h2>PPC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Board_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;PPC_7410_1&quot;</td><td>&quot;PPC_7410_1&quot;</td></tr><tr><td>Processor_Speed</td><td>500.0</td><td>500.0</td></tr><tr><td>Co_Processor_Name</td><td>&quot;Altivec_1&quot;</td><td>&quot;Altivec_1&quot;</td></tr><tr><td>Cache_Speed</td><td>500.0 /*MHz*/</td><td>500.0</td></tr><tr><td>Cache_Size</td><td>2000 /*KB*/</td><td>2000</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_1&quot;</td><td>&quot;Cache_1&quot;</td></tr><tr><td>Next_Memory</td><td>&quot;DDR3&quot;</td><td>&quot;DDR3&quot;</td></tr><tr><td>CoProcessor_Speed</td><td>Processor_Speed * 2 /*Range from 400-1300 */</td><td>1000.0</td></tr></table> <h2>Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;PPC&quot;</td><td>&quot;PPC&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set or File Path. */\\n Mnew Ra Rb Rc Rd Re ; /* Label */\\n PPC IU BPU FPU VPU ;\\n IU INT_1 INT_2 ;\\n BPU INT_3 ;\\n FPU FP_1 ;\\n VPU FP_2 ;\\n\\nbegin INT_1 ; /* Group */\\n IU_add 1 ;\\n IU_shift 1 ;\\n IU_rotate 1 ;\\n IU_logical 1 ;\\nend INT_1 ;\\n\\nbegin INT_2 ; /* Group */\\n IU_mux 6 ;\\n IU_div 19 ;\\nend INT_2 ;\\n\\nbegin INT_3 ; /* Group */\\n *b 1 ;\\n l_s 1 ;\\nend INT_3 ;\\n\\nbegin FP_1 ; /* Group */\\n FPU_s_add 3 ;\\n FPU_s_mul 3 ;\\n FPU_s_madd 3 ;\\n FPU_s_div 17 ;\\n FPU_d_add 3 ;\\n FPU_d_mul 3 ;\\n FPU_d_madd 3 ;\\n FPU_d_div 31 ;\\nend FP_1 ;\\n\\nbegin FP_2 ; /* Group */\\n vpu_sim_int 1 ;\\n vpu_com_int 3 ;\\n vpu_fp 4 ;\\nend FP_2 ;</td><td>/* Instruction Set or File Path. */\\n Mnew Ra Rb Rc Rd Re ; /* Label */\\n PPC IU BPU FPU VPU ;\\n IU INT_1 INT_2 ;\\n BPU INT_3 ;\\n FPU FP_1 ;\\n VPU FP_2 ;\\n\\nbegin INT_1 ; /* Group */\\n IU_add 1 ;\\n IU_shift 1 ;\\n IU_rotate 1 ;\\n IU_logical 1 ;\\nend INT_1 ;\\n\\nbegin INT_2 ; /* Group */\\n IU_mux 6 ;\\n IU_div 19 ;\\nend INT_2 ;\\n\\nbegin INT_3 ; /* Group */\\n *b 1 ;\\n l_s 1 ;\\nend INT_3 ;\\n\\nbegin FP_1 ; /* Group */\\n FPU_s_add 3 ;\\n FPU_s_mul 3 ;\\n FPU_s_madd 3 ;\\n FPU_s_div 17 ;\\n FPU_d_add 3 ;\\n FPU_d_mul 3 ;\\n FPU_d_madd 3 ;\\n FPU_d_div 31 ;\\nend FP_1 ;\\n\\nbegin FP_2 ; /* Group */\\n vpu_sim_int 1 ;\\n vpu_com_int 3 ;\\n vpu_fp 4 ;\\nend FP_2 ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>HW_DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;DDR3&quot;</td><td>&quot;DDR3&quot;</td></tr><tr><td>HW_DRAM_Speed_Mhz</td><td>400.0</td><td>400.0</td></tr><tr><td>Number_of_Banks</td><td>8</td><td>8</td></tr><tr><td>Sim_Time</td><td>1.0E-05</td><td>1.0E-5</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td></tr><tr><td>Memory_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Burst_Length</td><td>8 /* 2, 4, 8 */</td><td>8</td></tr><tr><td>DRAM_Type</td><td>&quot;DDR3&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2, DDR3 */</td><td>&quot;DDR3&quot;</td></tr><tr><td>Mfg_Suggest_Timing</td><td>{2,2,2,6} /* tCAS, tRCD, tRP, tRAS */</td><td>{2, 2, 2, 6}</td></tr><tr><td>Extra_Timing</td><td>{2,2,1,1,3,1,2,1,0,16} /* DQSS, tWTR, tRRD, tWR, tRL, tWL , tDQSCK, tRTP, tHWpre, tFAW */</td><td>{2, 2, 1, 1, 3, 1, 2, 1, 0, 16}</td></tr><tr><td>Fix_DQSS</td><td>true</td><td>true</td></tr><tr><td>Refresh_Rate_per_Bank_ms</td><td>64.0 /* 64.0 ms */</td><td>64.0</td></tr><tr><td>Refresh_Cycles_per_Bank</td><td>256 /* 256 cycles per bank */</td><td>256</td></tr><tr><td>Enable_External_Data</td><td>false</td><td>false</td></tr><tr><td>Address_Bit_Map</td><td>{{0,9},{10,24},{25,27}} /* col, row, bank (min, max) Bit Position */</td><td>{{0, 9}, {10, 24}, {25, 27}}</td></tr><tr><td>Standard_Name</td><td>&quot;none&quot; /*reads DDR_Memory_Standards.txt */</td><td>&quot;none&quot;</td></tr><tr><td>Standard_File</td><td>VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt</td><td>&quot;VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Memory_Controller</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Bank_at_a_Time</td><td>true /* false=all */</td><td>true</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr></table> <h2>DDR</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Controller_Name</td><td>&quot;DDR&quot;</td><td>&quot;DDR&quot;</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR2_S2&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR2_S2&quot;</td></tr><tr><td>Controller_Speed_Mhz</td><td>400.0</td><td>400.0</td></tr><tr><td>Memory_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Bus_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Command_Buffer_Length</td><td>8</td><td>8</td></tr><tr><td>Commands_in_a_Row</td><td>8</td><td>8</td></tr><tr><td>Mfg_Suggest_Timing</td><td>{3,7,8,17} /* tCL, tRCD, tRP, tRAS */</td><td>{3, 7, 8, 17}</td></tr><tr><td>Extra_Timing</td><td>{1,3,4,1,3,1,1,1,0} /* DQSS, tWTR, tRRD,tWR, tRL, tWL, tDQSCK, tRTP, tHWpre */</td><td>{1, 3, 4, 1, 3, 1, 1, 1, 0}</td></tr><tr><td>Burst_Length</td><td>8 /* 2, 4, 8 */</td><td>8</td></tr><tr><td>Memory_Column</td><td>{8,29} </td><td>{8, 29}</td></tr><tr><td>Memory_Row</td><td>{4,7} </td><td>{4, 7}</td></tr><tr><td>Memory_Bank</td><td>{30,31}</td><td>{30, 31}</td></tr><tr><td>Memory_Bank_Length</td><td>round(pow(2,(Memory_Bank(1) - Memory_Bank(0) + 1)))</td><td>4L</td></tr><tr><td>DRAM_Return_Cycles</td><td>0</td><td>0</td></tr><tr><td>First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Sim_Time</td><td>1.0E-05</td><td>1.0E-5</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>DEBUG</td><td>true</td><td>true</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;DDR0&quot;</td><td>&quot;DDR0&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr></table> <h2>Bridge2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge2&quot;</td><td>&quot;Bridge2&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>1.0</td><td>1.0</td></tr></table> <h2>Bridge</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge&quot;</td><td>&quot;Bridge&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>1.0</td><td>1.0</td></tr></table> <h2>AXI_Bus</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_Top&quot;</td><td>&quot;AXI_Top&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>1000.0</td><td>1000.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>1.0E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>2</td><td>2</td></tr><tr><td>Write_Threshold</td><td>2</td><td>2</td></tr><tr><td>Master_Request_Threshold</td><td>{2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2} </td><td>{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>8</td><td>8</td></tr><tr><td>Number_Slaves</td><td>3</td><td>3</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>true</td><td>true</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>2</td><td>2</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;DDR3&quot;},{&quot;SDRAM&quot;},{&quot;DRAM3&quot;},{&quot;Device_4&quot;}}</td><td>{{&quot;DDR3&quot;}, {&quot;SDRAM&quot;}, {&quot;DRAM3&quot;}, {&quot;Device_4&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{false,false,true,false,false,false,false,false}</td><td>{false, false, true, false, false, false, false, false}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{true,false,false,false} </td><td>{true, false, false, false}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr></table>